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Remote Asic Physical Design Engineer Jobs (NOW HIRING)

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...

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Remote Asic Physical Design Engineer information

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$95K

$141.5K

How much do remote asic physical design engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for remote asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What does a remote ASIC physical design engineer do?

A Remote ASIC Physical Design Engineer is responsible for transforming circuit designs into physical layouts that can be manufactured as integrated circuits (ICs), specifically Application-Specific Integrated Circuits (ASICs). Their role includes tasks such as floorplanning, placement, routing, timing analysis, and verifying that the physical design meets performance and power specifications. Working remotely, they collaborate with design and verification teams using specialized EDA (Electronic Design Automation) tools to optimize chip layouts for manufacturability and efficiency. Effective communication and expertise in physical design processes are essential for success in this role.

What are the key skills and qualifications needed to thrive as a remote ASIC physical design engineer?

To thrive as a Remote ASIC Physical Design Engineer, you need a strong background in digital logic design, ASIC implementation, and a relevant engineering degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as scripting languages like TCL and Python, is typically required. Excellent problem-solving, communication, and time management skills are vital for effective remote collaboration and project delivery. These skills and qualifications ensure high-quality chip designs, efficient workflow, and seamless teamwork in a distributed environment.

What are some common challenges faced by a remote ASIC physical design engineer, and how can they be addressed?

Remote ASIC Physical Design Engineers often encounter challenges related to communication and collaboration, especially when coordinating with cross-functional teams such as verification, synthesis, and EDA tool support. Time zone differences and limited face-to-face interaction can make it harder to quickly resolve design issues or clarify specifications. To overcome these challenges, engineers should leverage collaborative tools, maintain clear documentation, and proactively schedule regular check-ins with team members. Building strong virtual communication habits helps ensure smooth project execution and timely delivery of design milestones.
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Remote Asic Physical Design Engineer jobs near you
Infographic showing various Remote Asic Physical Design Engineer job openings in the United States as of September 2026, with employment types broken down into 79% Full Time, and 21% Contract. Highlights an 100% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Boston, MA • On-site, Remote

Encore Semi, Inc.
Semiconductor and Electronic Component Manufacturing • 51 - 200 employees
Learn more about Encore Semi, Inc.external

$150K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired 2 days ago. Applications are no longer accepted.

Job description

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.
We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.
Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).
  • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).
  • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.
  • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.
  • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).
  • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows.
Qualifications:
  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm).
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures.
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime.
  • Strong scripting skills (Tcl, Python, Bash).
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre.

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
•15 days of PTO per calendar year
•10 paid Holidays per calendar year
•Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
•Dental & Vision: Company covers 50% of premiums for Employee and Dependents
•Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
•Employee Assistant Program (EAP)
•401k - Traditional & Roth
•Life/AD&D and Long-Term Disability
•Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/

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