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Remote Asic Physical Design Engineer Jobs (NOW HIRING)

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs * Build and optimize EDA infrastructure ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs * Build and optimize EDA infrastructure ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · On-site +1

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... Strong interpersonal skills and ability to work with on-site and remote teams NVIDIA is widely ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

K2 Space

Principal ASIC Design Verification Engineer

$190K - $285K/yr

Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...

Evs

Substation Physical Design Engineer

Eden Prairie, MN · On-site +1

$85K - $120K/yr

Eden Prairie, MN | Hybrid | Remote Schedule: Full-Time Salary: $85,000 - $120,000 (based on experience) EVS is seeking a Substation Physical Design Engineer to support the design and delivery of ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ... Engineering, or related field. * 5+ years of experience in ASIC/SoC verification. * Solid ...

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How much do remote asic physical design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for remote asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What does a remote ASIC physical design engineer do?

A Remote ASIC Physical Design Engineer is responsible for transforming circuit designs into physical layouts that can be manufactured as integrated circuits (ICs), specifically Application-Specific Integrated Circuits (ASICs). Their role includes tasks such as floorplanning, placement, routing, timing analysis, and verifying that the physical design meets performance and power specifications. Working remotely, they collaborate with design and verification teams using specialized EDA (Electronic Design Automation) tools to optimize chip layouts for manufacturability and efficiency. Effective communication and expertise in physical design processes are essential for success in this role.

What are some common challenges faced by a remote ASIC physical design engineer, and how can they be addressed?

Remote ASIC Physical Design Engineers often encounter challenges related to communication and collaboration, especially when coordinating with cross-functional teams such as verification, synthesis, and EDA tool support. Time zone differences and limited face-to-face interaction can make it harder to quickly resolve design issues or clarify specifications. To overcome these challenges, engineers should leverage collaborative tools, maintain clear documentation, and proactively schedule regular check-ins with team members. Building strong virtual communication habits helps ensure smooth project execution and timely delivery of design milestones.

What are the key skills and qualifications needed to thrive as a remote ASIC physical design engineer?

To thrive as a Remote ASIC Physical Design Engineer, you need a strong background in digital logic design, ASIC implementation, and a relevant engineering degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as scripting languages like TCL and Python, is typically required. Excellent problem-solving, communication, and time management skills are vital for effective remote collaboration and project delivery. These skills and qualifications ensure high-quality chip designs, efficient workflow, and seamless teamwork in a distributed environment.
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Remote Asic Physical Design Engineer jobs near you
Infographic showing various Remote Asic Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 82% Full Time, 6% Part Time, and 12% Contract. Highlights an 100% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

ASIC Engineer, Power

Meta

Sunnyvale, CA • On-site, Remote

$146K/yr

Full-time

Posted 15 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

136th of 242 rated software companies

Job description

Meta is building custom silicon to power the infrastructure that underlies its family of products and services. As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and maintain power analysis and optimization flows that enable silicon engineers across the organization to accurately model, estimate, and reduce power consumption in custom ASIC designs. In this role, you will work at the intersection of EDA tooling, physical design, and power methodology, helping to define the infrastructure that shapes how Meta's next-generation chips are designed and verified.
ASIC Engineer, Power Responsibilities:
  • Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools
  • Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow
  • Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs
  • Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround time
  • Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations
  • Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages
  • Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders
  • Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities
  • Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques
  • Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Minimum Qualifications:
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff
  • Experience developing or maintaining EDA flows for power analysis using tools such as Synopsys PrimePower, Cadence Voltus, or equivalent
  • Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows
  • Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows
  • Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs

Preferred Qualifications:
  • Experience evaluating and qualifying new EDA tools or methodologies in a production silicon environment
  • Familiarity with custom or semi-custom design flows for high-performance computing or data center silicon
  • Experience with low-power design techniques including clock gating, power gating, multi-voltage domain design, and dynamic voltage and frequency scaling
  • Background in developing internal EDA infrastructure tooling or flow automation at scale across multiple concurrent design projects

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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