You will develop robust compact models for active and passive components, ensuring that our ... Experience in taping out and testing large-scale photonic integrated circuits, including ...
You will develop robust compact models for active and passive components, ensuring that our ... Experience in taping out and testing large-scale photonic integrated circuits, including ...
You will develop robust compact models for active and passive components, ensuring that our ... Experience in taping out and testing large-scale photonic integrated circuits, including ...
You will develop robust compact models for active and passive components, ensuring that our ... Experience in taping out and testing large-scale photonic integrated circuits, including ...
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Psl Scale For Modeling information
See salary details
$11K - $19.6K
0% of jobs
$19.6K - $28.2K
0% of jobs
$28.2K - $36.8K
0% of jobs
$36.8K - $45.4K
0% of jobs
$45.4K - $54K
0% of jobs
$54K - $62.5K
0% of jobs
$62.5K - $71.1K
0% of jobs
$71.1K - $79.7K
0% of jobs
$79.7K - $88.3K
0% of jobs
$91.6K is the 25th percentile. Wages below this are outliers.
$88.3K - $96.9K
65% of jobs
$99.4K is the 75th percentile. Wages above this are outliers.
$96.9K - $105.5K
35% of jobs
$11K
$105.5K
How much do psl scale for modeling jobs pay per year?

Full-time
Re-posted 10 days ago
Job description
We are hiring a Photonics PDK Modeling Engineer to join our team. In this role, you will lead the development of our internal Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between physical device physics and system-level simulation. You will develop robust compact models for active and passive components, ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, applying software engineering rigor to the challenges of photonic hardware design.
Responsibilities- Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models.
- Create and verify behavioral compact models for passive and active devices
- Simulation Infrastructure: Build automated workflows that extract parameters from electromagnetic solvers (FDTD/FEM) and package them into the PDK for circuit-level simulation.
- Model-Hardware Correlation: Validate simulation models against lab measurements. Perform data fitting and statistical analysis to align model parameters with real-world silicon performance.
- Automated Verification: Implement regression testing and Continuous Integration (CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic.
- Netlist & Connectivity: Own the logic for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent.
- Master's +5 years experience or PhD +3 years experience in Electrical Engineering, Photonics, Physics, or related field.
- Deep understanding of photonic device physics and experience in device simulation.
- Experience building behavioral models for circuit simulators (e.g., Lumerical INTERCONNECT, Cadence, Synopsys OptSim, or custom Python solvers).
- Experienced in Python for modeling, automation, and data analysis. Comfortable with object-oriented programming and scientific libraries (NumPy, SciPy).
- Python based layout experience.
- Familiarity with GDSFactory, OptoCompiler or KLayout Python scripting.
- Experience with Python-native circuit simulation ecosystems (e.g., SAX, Photontorch, Simphony).
- Experience with Git version control, unit testing (pytest), and CI/CD workflows.
- Prior experience in performing physical layout using foundry-provided process design kits (PDKs), adhering to specific design rules and constraints.
- Experience in taping out and testing large-scale photonic integrated circuits, including familiarity with relevant testing equipment and methodologies.
- Experience doing inverse design
- Possess strong project execution skills, demonstrating the ability to effectively manage multiple design priorities, adhere to project timelines, and meet critical milestones.