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Pnr Physical Design Engineer Jobs (NOW HIRING)

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical design, identify potential solutions, and drive execution. - Drive optimization of PnR ... Engineering or related field. Experience with partition level P&R implementation including ...

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

Description - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. - You will also collaborate ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical design, identify potential solutions, and drive execution. - Drive optimization of PnR ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

Description - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. - You will also collaborate ...

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

... physical design, identify potential solutions, and drive execution. • Drive optimization of PnR ... Computer Engineering or related field Experience with large SOC designs (>20M gates) with ...

Apple

SoC Physical Design Engineer, PnR

Waltham, MA · On-site

$146K - $151K/yr

Description - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. - You will also collaborate ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical design, identify potential solutions, and drive execution. • Drive optimization of PnR ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical design, identify potential solutions, and drive execution. • Drive optimization of PnR ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

Description • You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off • You will also ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...

Apple

CPU Physical Design Engineer

Santa Clara, CA · On-site

$150K - $277K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • ... PNR tool features and optimizations and their adoption in CPU design • Will work with x ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...

Apple

SoC Physical Design Engineer, PnR

Waltham, MA · On-site

$146K - $151K/yr

... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...

Apple

CPU Physical Design Engineer

Santa Clara, CA · On-site

$150K - $277K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • ... PNR tool features and optimizations and their adoption in CPU design • Will work with x ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$175K - $308K/yr

... physical design, identify potential solutions, and drive execution. - Drive optimization of PnR ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

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Pnr Physical Design Engineer information

See salary details

$95K

$141.5K

How much do pnr physical design engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for pnr physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a Pnr Physical Design Engineer?

PnR Physical Design Engineers, or Place and Route Physical Design Engineers, are professionals who work on the physical implementation of integrated circuit (IC) designs. They are responsible for converting logical circuit designs into layouts that can be manufactured on silicon chips, ensuring optimal placement and routing of components to meet performance, power, and area requirements. Their work involves using Electronic Design Automation (EDA) tools to address challenges such as signal timing, power distribution, and manufacturability. This role is critical in the semiconductor industry, particularly in the development of CPUs, GPUs, and ASICs.

What are the key skills and qualifications needed to thrive as a Pnr Physical Design Engineer, and why are they important?

To thrive as a PnR Physical Design Engineer, you need a solid background in VLSI design, digital electronics, and experience with CMOS technology, often supported by a degree in electrical engineering or a related field. Expertise in EDA tools such as Cadence Innovus, Synopsys ICC2, and knowledge of scripting languages like TCL or Perl are typically required. Strong problem-solving, attention to detail, and effective communication are essential soft skills in this field. These competencies ensure high-performance, manufacturable chip designs while meeting strict timing, power, and area constraints in semiconductor development.

What are some common challenges faced by Pnr Physical Design Engineers during tapeout, and how can they be addressed?

PnR Physical Design Engineers often encounter challenges such as timing closure, congestion management, and meeting power targets during the tapeout phase. These issues can be addressed by closely collaborating with the front-end design and verification teams, optimizing floorplanning, and utilizing advanced EDA tools for iterative improvements. Proactive identification of critical paths and effective communication with stakeholders are essential to ensure successful tapeout within project timelines.

What is the difference between Pnr Physical Design Engineer vs ASIC Physical Design Engineer?

AspectPnr Physical Design EngineerASIC Physical Design Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, VLSI DesignBachelor's or Master's in Electrical/Electronic Engineering, VLSI Design
Work EnvironmentSemiconductor companies, EDA tool environments, chip design teamsSemiconductor companies, EDA tool environments, chip design teams
Industry UsageUsed during the final stages of chip layout to ensure timing and routingUsed throughout the entire ASIC design process, including logic to physical implementation

The Pnr Physical Design Engineer specializes in the placement and routing phase of chip design, focusing on physical implementation and timing closure. In contrast, the ASIC Physical Design Engineer covers a broader scope, including logic synthesis, floorplanning, and physical design. Both roles require similar skills and work environments but differ in their specific responsibilities within the ASIC design flow.

What are popular job titles related to Pnr Physical Design Engineer jobs?

For Pnr Physical Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Pnr Physical Design Engineer job openings in the United States as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

SoC Physical Design Engineer, PnR

Beaverton, OR • On-site

Apple
Computer and Electronic Product Manufacturing • 10K+ employees
Learn more about Appleexternal

$141K - $145K/yr

Full-time

Re-posted 11 days ago

Apple rating

8.1

Company rating: 8.1 out of 10

Based on 684 frontline employees who took The Breakroom Quiz

6th of 30 rated technology retailers

Job description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Description
- Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- Timing, physical and electrical verification, and driving the signoff closure for the partitions.
- Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
- Drive optimization of PnR partitions, to achieve best Power/Performance/Area.
Minimum Qualifications
Minimum BS and 0+ years of industry experience
Preferred Qualifications
MS in Electrical/Electronics/Computer Engineering or related field.
Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
Experience with physical design construction and analysis flows and methodology.
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
Familiar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategies.
Experience with industry standard tools, understanding their capabilities and underlying algorithms.
Experience with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration.
From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.
Ability to adhere to stringent schedule and die size requirements.
Strong communication skills.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

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