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Staff Physical Design Engineer Jobs (NOW HIRING)

Qualcomm

Staff. Physical Design Engineer

San Diego, CA · On-site

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... Staffing and recruiting agencies and individuals being represented by an agency are not authorized ...

Tenstorrent

Staff Physical Design Engineer

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from ...

Qualcomm

Staff. Physical Design Engineer

Santa Clara, CA · On-site

$150 - $200/hr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

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Lightmatter

Sr. Staff Physical Design Engineer

Boston, MA · On-site

$147K - $152K/yr

We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of complex digital blocks. In this role, you will leverage your expertise in advanced process nodes (3nm ...

Lightmatter

Sr. Staff Physical Design Engineer

Boston, MA · On-site

$217K - $267K/yr

We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of complex digital blocks. In this role, you will leverage your expertise in advanced process nodes (3nm ...

Micron

Staff Physical Design Engineer, HBM

Richardson, TX · On-site

$123K - $127K/yr

Micron's HighBandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of highperformance, lowpower digital logic used in ...

search-tactics

Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is okay C2C Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

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Staff Physical Design Engineer information

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$52.5K

$150.6K

$187.5K

How much do staff physical design engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for staff physical design engineer in the United States is $150,620.00, according to ZipRecruiter salary data. Most workers in this role earn between $142,000.00 and $171,000.00 per year, depending on experience, location, and employer.

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Staff Physical Design Engineer jobs near you
Infographic showing various Staff Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 17% Part Time, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $150,620 per year, or $72.4 per hour.

Staff / Senior Staff Physical Design Engineer

Sunnyvale, CA • On-site

Bolt Graphics, Inc.
See more jobs at Bolt Graphics, Inc.external

$200 - $250/hr

Other

Medical, Dental, Vision, Retirement

Re-posted 24 days ago

Job description

Staff / Senior Staff Physical Design Engineer

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values
  • Be Fearless: Unmute yourself. Test boundaries and get proven right.
  • Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
  • Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:

As a Staff / Senior Staff Physical Design Engineer , you will be responsible for driving full-chip or block-level physical implementation from netlist to GDSII. You will play a critical role in achieving timing, power, and area (PPA) targets while ensuring high-quality tapeouts.

What you'll do:

  • Ownend-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing, and signoff
  • Drivetiming closure(setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV)
  • Perform and debugDRC/LVS/EM/IRissues and drive clean signoff
  • Work closely with RTL, architecture, and verification teams fordesign convergence
  • HandleECO flows, including late-stage timing and functional fixes
  • Optimize designs forpower, performance, and area (PPA)
  • Integrate and validatehard macros (SRAMs, IOs, analog blocks)
  • SupportGLS, SDF generation, and debug timing-related issues
  • Develop and enhanceautomation scripts(TCL/Python) for PD flows
  • Collaborate with foundry/vendor teams duringtapeout and signoff

Required Qualifications:

  • Bachelor’s/Master’s degree in Electrical Engineering or related field
  • 8–12 years of experiencein ASIC physical design
  • Proven experience infull-chip or large block implementation and tapeouts
  • Strong expertise in:
  • Floorplanning and power planning
  • Placement, CTS, routing, and physical verification
  • Static Timing Analysis (STA) and timing closure
  • Hands‑on experience with industry‑standard tools such as:
  • Synopsys ICC2/Cadence Innovus
  • Experience with advanced nodes (7nm and below preferred)
  • Strong debugging and problem‑solving skills

Preferred Qualifications:

  • Experience withlow-power design techniques (UPF/CPF)
  • Knowledge ofEMIR analysis(e.g.,Ansys RedHawk‑SC)
  • Familiarity withmulti-voltage designs and power domains
  • Experience withhigh-speed interfaces or complex SoCs (CPU/GPU/AI)
  • Exposure toGLS and timing‑related silicon debug
  • Scripting expertise inPython/TCL

Compensation Range: $200,000–$220,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.

  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

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