You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.
You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.
Staff PCIe Design Engineer
Toronto, ON · Hybrid
CA$159K - CA$215K/yr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Staff PCIe Design Engineer
Toronto, ON · Hybrid
CA$159K - CA$215K/yr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Senior PCIe Design Engineer
Toronto, ON · Hybrid
CA$125K - CA$170K/yr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Senior PCIe Design Engineer
Toronto, ON · Hybrid
CA$125K - CA$170K/yr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Staff PCIe Design Engineer
Toronto, ON · On-site
$159.40 - $215.60/hr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Staff PCIe Design Engineer
Toronto, ON · On-site
$159.40 - $215.60/hr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Senior PCIe Design Engineer
Toronto, ON · On-site
$125.80 - $170.20/hr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
Senior PCIe Design Engineer
Toronto, ON · On-site
$125.80 - $170.20/hr
As a creative design engineer with a knowledge of I/O subsystems, SoCs you will be part of a team ... DFT and physical implementation In Return We are proud to have a set of behaviors that reflect our ...
... Engineering organization. CDFX has a global footprint with design teams located in several AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
... Engineering organization. CDFX has a global footprint with design teams located in several AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Sr. RTL Design Engineer
Thornhill, ON · Hybrid
ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Sr. RTL Design Engineer
Thornhill, ON · Hybrid
ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Sr. RTL Design Engineer
Thornhill, ON · Hybrid
ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Sr. RTL Design Engineer
Thornhill, ON · Hybrid
ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including ... mental or physical disability, national origin, race, religion, political and/or third-party ...
... Engineering organization. CDFX has a global footprint with design teams located in several AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
... Engineering organization. CDFX has a global footprint with design teams located in several AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
You will develop a strong foundation in industry best practices for schematic design, physical ... Work closely with engineers within Markham and other AMD design sites worldwide to enable solutions ...
You will develop a strong foundation in industry best practices for schematic design, physical ... Work closely with engineers within Markham and other AMD design sites worldwide to enable solutions ...
AMD Mixed Signal IP Design Analysis and CAD Engineer will learn: * The hardware chip development ... Use industry standard physical verification analysis tools to analyze hardware design components ...
AMD Mixed Signal IP Design Analysis and CAD Engineer will learn: * The hardware chip development ... Use industry standard physical verification analysis tools to analyze hardware design components ...
Mixed Signal Circuit Design Analysis & CAD Engineer (Temporary 1 Year Contract)
Thornhill, ON · Hybrid
AMD Mixed Signal IP Design Analysis and CAD Engineer will learn: * The hardware chip development ... Use industry standard physical verification analysis tools to analyze hardware design components ...
Mixed Signal Circuit Design Analysis & CAD Engineer (Temporary 1 Year Contract)
Thornhill, ON · Hybrid
AMD Mixed Signal IP Design Analysis and CAD Engineer will learn: * The hardware chip development ... Use industry standard physical verification analysis tools to analyze hardware design components ...
Mixed Signal Circuit Design Analysis & CAD Engineer ( Temporary 1 Year Contract)
Thornhill, ON · On-site
You will develop a strong foundation in industry best practices for schematic design, physical ... Work closely with engineers within Markham and other AMD design sites worldwide to enable solutions ...
Mixed Signal Circuit Design Analysis & CAD Engineer ( Temporary 1 Year Contract)
Thornhill, ON · On-site
You will develop a strong foundation in industry best practices for schematic design, physical ... Work closely with engineers within Markham and other AMD design sites worldwide to enable solutions ...
Key Responsibilities Lead and own the physical layout design of complex analog/mixed-signal macros ... engineers/contractors across multiple time zones, enforcing best practices in layout design and ...
Key Responsibilities Lead and own the physical layout design of complex analog/mixed-signal macros ... engineers/contractors across multiple time zones, enforcing best practices in layout design and ...
We are looking for a Staff Digital Design Engineer to help define, build, and optimize high ... How cross-functional workflows come together across design, DV, physical, and firmware teams.
We are looking for a Staff Digital Design Engineer to help define, build, and optimize high ... How cross-functional workflows come together across design, DV, physical, and firmware teams.
Analog and RF Layout Engineer
Toronto, ON · On-site
At Capgemini Engineering, the world leader in engineering services, we bring together a global team ... Collaborate closely with Analog, RF, Digital, Physical Design, Verification, and Process teams to ...
Analog and RF Layout Engineer
Toronto, ON · On-site
At Capgemini Engineering, the world leader in engineering services, we bring together a global team ... Collaborate closely with Analog, RF, Digital, Physical Design, Verification, and Process teams to ...
... physical products. * proven ability to apply mechanical and manufacturing engineering fundamentals to successfully solve complex design challenges. * the ability to communicate complex and abstract ...
Quick apply
... physical products. * proven ability to apply mechanical and manufacturing engineering fundamentals to successfully solve complex design challenges. * the ability to communicate complex and abstract ...
Static Timing Analysis (STA) Engineer
Toronto, ON · On-site
CA$102K - CA$149K/yr
... physical design teams. * Constraint Development: Assist in developing and validating timing ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Static Timing Analysis (STA) Engineer
Toronto, ON · On-site
CA$102K - CA$149K/yr
... physical design teams. * Constraint Development: Assist in developing and validating timing ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Systems Design Engineer
Thornhill, ON · On-site
We are searching for a Firmware Engineer to help with developing ,debugging and resolving AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
Systems Design Engineer
Thornhill, ON · On-site
We are searching for a Firmware Engineer to help with developing ,debugging and resolving AMD ... mental or physical disability, national origin, race, religion, political and/or third-party ...
... physical products. * proven ability to apply mechanical and manufacturing engineering fundamentals to successfully solve complex design challenges. * the ability to communicate complex and abstract ...
... physical products. * proven ability to apply mechanical and manufacturing engineering fundamentals to successfully solve complex design challenges. * the ability to communicate complex and abstract ...
Physical Design Engineer information
See Ontario salary details
$23.56 - $31.73
3% of jobs
$31.73 - $39.90
0% of jobs
$39.90 - $48.08
2% of jobs
$48.08 - $56.25
7% of jobs
$64.25 is the 25th percentile. Wages below this are outliers.
$56.25 - $64.42
13% of jobs
$64.42 - $72.60
16% of jobs
The median wage is $76.07 / hr.
$72.60 - $80.77
21% of jobs
$86.66 is the 75th percentile. Wages above this are outliers.
$80.77 - $88.94
18% of jobs
$88.94 - $97.12
6% of jobs
$97.12 - $105.29
5% of jobs
$105.29 - $113.46
8% of jobs
$23
$77
$113
How much do physical design engineer jobs pay per hour?
What is a physical design engineer?
A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.
What are the typical daily responsibilities of a physical design engineer?
As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.
What are the key skills and qualifications needed to thrive as a physical design engineer?
To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.
What are the most commonly searched types of Physical Design Engineer jobs in Ontario?
The most popular types of Physical Design Engineer jobs in Ontario are:
What are popular job titles related to Physical Design Engineer jobs in Ontario?
For Physical Design Engineer jobs in Ontario, the most frequently searched job titles are:
What job categories do people searching Physical Design Engineer jobs in Ontario look for?
The top searched job categories for Physical Design Engineer jobs in Ontario are:
What are popular job titles related to Physical Design Engineer jobs in ON?
For Physical Design Engineer jobs in ON, the most frequently searched job titles are:

Full-time
Re-posted 10 days ago
Key responsibilities
Own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout.
Drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.
Partner with various teams and external partners to ensure cross-functional alignment, manage dependencies, and track program progress.
Job description
Role Overview
As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.
You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.
This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.
Key Responsibilities
Program Execution & Planning
- Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
- Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
- Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.
Cross-Functional Alignment & Coordination
- Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
- Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
- Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.
Risk Management & Decision-Making
- Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.
- Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.
Process & Operational Excellence
- Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.
Basic Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.
- Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
- Experience with advanced process nodes and high-performance ASIC/SoC development.
- Strong understanding of ASIC development milestones from product requirements through final GDS handoff.
- Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.
- Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.
- Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.
Preferred Qualifications
- Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
- Excellent communication, organizational, leadership, and stakeholder-management skills.
- Ability to influence without authority across global, cross-functional, and cross-cultural teams.
- Ability to operate independently in a fast-paced, ambiguous, high-growth environment.
- Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.
Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
About Astera Labs
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
11 - 50 Employees
Headquarters location
Santa Clara, CA, US
Year founded
2017