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Physical Design Engineer Intern Jobs in Oregon (NOW HIRING)

Microsoft

Senior Physical Design Engineer

Hillsboro, OR · On-site

$113K - $156K/yr

We are looking for a Senior Physical Design Engineer to join the team. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Engineering or related field. Experience with partition level P&R implementation including ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Nvidia

Senior CPU Design Engineer

Hillsboro, OR · Hybrid

You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be doing: * Drive the micro-architecture ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design ... Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Strong programming ...

Apple

SoC Physical Design Verification Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Description • As a member of our physical design team, you will perform various types of physical ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...

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Physical Design Engineer Intern information

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is a physical design engineer intern?

A physical design engineer intern is a student or entry-level professional gaining hands-on experience in the physical implementation of integrated circuits, including tasks like floorplanning, placement, routing, and timing analysis. They typically work with electronic design automation (EDA) tools and collaborate with engineering teams to optimize chip performance and manufacturability.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in Oregon?

The most popular types of Physical Design Engineer jobs in Oregon are:

What are popular job titles related to Physical Design Engineer Intern jobs in Oregon?

For Physical Design Engineer Intern jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Intern jobs in Oregon look for?

The top searched job categories for Physical Design Engineer Intern jobs in Oregon are:

What cities in Oregon are hiring for Physical Design Engineer Intern jobs?

Cities in Oregon with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you

Mid-level Physical Design Engineer CPU

Intel Corporation

Hillsboro, OR • On-site

$148K - $152K/yr

Full-time

Medical, Retirement, PTO

Re-posted 14 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:
Job Description:
About the Role
Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance, power-efficient silicon using advanced process technologies.
In this role, you will take on increasing ownership within the RTL-to-GDS flow, working on block-level implementation while collaborating closely with cross-functional teams. This position offers strong growth opportunities as you build depth in physical design and SoC development.
What You'll Do
Key responsibilities will include but not limited to:
  • Execute physical design implementation for CPU core blocks or subsystems
  • Perform synthesis, floor planning, place and route (PnR), and design closure activities
  • Conduct static timing analysis (STA), power analysis, and physical verification
  • Identify and debug timing, power, and design rule violations
  • Contribute to achieving timing, power, and area (PPA) targets
  • Develop and maintain scripts for design automation (e.g., TCL, Python)
  • Collaborate with RTL design, verification, clocking, and full-chip teams
  • Support improvements to design flows, methodologies, and best practices
  • Document technical work and share knowledge within the team

Behavioral traits that we are looking for:
  • Strong analytical and problem-solving skills
  • Takes ownership of assigned tasks and delivers with accountability
  • Works effectively in collaborative, cross-functional environments
  • Communicates technical information clearly and concisely
  • Shows adaptability in a fast-paced, evolving engineering environment
  • Demonstrates continuous learning and skill development

Why Join Us
  • Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
  • Be part of a team driving innovation at advanced semiconductor process nodes
  • Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design
  • Collaborate with experienced engineers across architecture, design, and full-chip integration
  • Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities
  • Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology
  • Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
    • See Intel Benefits for more details.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel's immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Bachelors in Computer / Electrical Engineering or related field with 5+ years of relevant work experience. Or a Masters in the same field with 3+ years of relevant work experience.
Your experience described above must be in the following:
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • PV convergence (including static timing and power analysis)
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
  • Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications and Experience:
  • Industry experience/exposure with CPU Micro-Architecture
  • Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Static Timing Analysis, Noise analysis, and reliability verification techniques
  • RTL to GDS methodologies and formal equivalence
  • Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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Benefits

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Workplace

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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