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Pattern Grading Jobs in California (NOW HIRING)

Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns. * MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory ...

Hands on experience with trouble shooting production, pattern and grading issues * Must have strong mastery and command of Excel and Adobe Illustrator * Must be proficient in Microsoft Office

Review graded nest patterns and issue grading guidelines to vendors post-fit approval to maintain consistent fit and quality. * Partner with Quality Control to creatively solve quality control issues ...

Sr. Technical Designer

Vernon, CA Β· On-site

$100K - $120K/yr

Review graded nest patterns and issue grading guidelines to vendors post-fit approval to maintain consistent fit and quality. * Partner with Quality Control to creatively solve quality control issues ...

Sr. Technical Designer

Vernon, CA Β· On-site

$100K - $120K/yr

Review graded nest patterns and issue grading guidelines to vendors post-fit approval to maintain consistent fit and quality. * Partner with Quality Control to creatively solve quality control issues ...

... pattern and grading issues * β€’ Must have strong mastery and command of Excel and Adobe Illustrator * β€’ Must be proficient in Microsoft Office * β€’ Intermediate experience for grading skills ...

Teaching Assitant

San Jose, CA

$16.50 - $20.75/hr

... and pattern recognition * Should be able to explain basic arithmetic facts and help students to make corrections * Grading homework and classwork , and recording grades * Candidates must be ...

Teaching Assitant

San Jose, CA Β· On-site

$16.50 - $20.75/hr

... and pattern recognition * Should be able to explain basic arithmetic facts and help students to make corrections * Grading homework and classwork , and recording grades * Candidates must be ...

Technical Designer

Irvine, CA Β· On-site

$90K - $95K/yr

Overall execution of fit, grading & construction while maintaining optimum quality from initial prototype development through production approval * Creates & provides pattern and/or pattern direction ...

Technical Designer

Burbank, CA Β· On-site

$80K - $90K/yr

Provide technical guidance on pattern corrections, grading, construction methods, and fabric performance * Review and approve tech packs, specs, BOMs, and measurement standards * Support vendor ...

Technical Designer

Irvine, CA Β· On-site

$90K - $95K/yr

Overall execution of fit, grading & construction while maintaining optimum quality from initial prototype development through production approval * Creates & provides pattern and/or pattern direction ...

Advanced knowledge of garment fit, measurement methodology, garment construction, pattern relationships, tolerances, and production quality standards. * Strong working knowledge of garment grading ...

Senior Techical Designer - Bras

City Of Industry, CA Β· Hybrid

$101K - $107K/yr

Review and approve bra patterns and pad molds/slopers, making pattern adjustments when necessary to achieve optimal fit and performance. * Ensure consistency in bra fit, grading, construction, and ...

Senior Techical Designer - Bras

City Of Industry, CA Β· Hybrid

$101K - $107K/yr

Review and approve bra patterns and pad molds/slopers, making pattern adjustments when necessary to achieve optimal fit and performance. * Ensure consistency in bra fit, grading, construction, and ...

Senior Techical Designer - Bras

City Of Industry, CA Β· Hybrid

$102K - $110K/yr

Review and approve bra patterns and pad molds/slopers, making pattern adjustments when necessary to achieve optimal fit and performance. * Ensure consistency in bra fit, grading, construction, and ...

Senior Techical Designer - Bras

City Of Industry, CA Β· On-site

$102K - $110K/yr

Review and approve bra patterns and pad molds/slopers, making pattern adjustments when necessary to achieve optimal fit and performance. * Ensure consistency in bra fit, grading, construction, and ...

Showing results 21-40

Pattern Grading information

What is a pattern grading?

A Pattern Grading job involves resizing a master pattern to create different sizes while maintaining the original design and fit. Pattern graders use manual techniques or computer software to adjust measurements and proportions systematically. This role is crucial in the fashion and apparel industry to ensure consistent sizing across garments. It requires a strong understanding of fabric behavior, technical specifications, and grading rules. Skilled pattern graders help streamline production by providing accurate patterns for mass manufacturing.

What does a pattern grader do?

Pattern Graders spend much of their day analyzing original patterns and systematically adjusting them into a range of sizes to ensure accurate fit across the intended size spectrum. They frequently use specialized software to create digital pattern files and must carefully check their work for consistency and quality. Collaboration is keyβ€”they often work closely with designers, sample makers, and the production team to interpret specifications and resolve any fit or construction issues. This role involves balancing technical precision with open communication to meet production timelines and maintain garment standards.

What skills and qualifications are needed for pattern grading?

To thrive as a Pattern Grader, you should have a strong understanding of garment construction, mathematics, and pattern-making principles, often backed by a degree or certification in fashion design or garment technology. Proficiency with computer-aided design (CAD) software such as Gerber, Lectra, or Optitex is typically required, along with experience in manual grading techniques. Attention to detail, strong organizational skills, and effective communication help Pattern Graders excel in collaborating with design and production teams. These abilities ensure accurate sizing, fit consistency, and efficient coordination, which are vital for successful apparel manufacturing.

How much does a pattern grader make?

Pattern graders typically earn between $30,000 and $60,000 annually, depending on experience, location, and the complexity of the garments they work on. Entry-level positions may start lower, while experienced pattern graders with advanced skills can earn higher salaries. The role often requires proficiency in pattern-making software and knowledge of garment construction.

What are the most commonly searched types of Pattern Grading jobs in California?

The most popular types of Pattern Grading jobs in California are:

What are popular job titles related to Pattern Grading jobs in California?

For Pattern Grading jobs in California, the most frequently searched job titles are:

What job categories do people searching Pattern Grading jobs in California look for?

The top searched job categories for Pattern Grading jobs in California are:

What cities in California are hiring for Pattern Grading jobs?

Cities in California with the most Pattern Grading job openings:

Infographic showing various Pattern Grading job openings in California as of September 2026, with employment types broken down into 1% Internship, 72% Full Time, 24% Part Time, 1% Temporary, and 2% Contract. Highlights an 88% Physical, 2% Hybrid, and 10% Remote job distribution.

DFT Engineer

Sunnyvale, CA β€’ On-site

Other

Posted 13 days ago


Key responsibilities

  • Define, implement, and optimize DFT architectures including Scan, ATPG, MBIST, and JTAG standards.

  • Perform scan chain insertion, stitching, and optimization to ensure timing closure and power compatibility.

  • Generate and validate high-coverage ATPG patterns and support post-silicon bring-up and debugging.


Job description

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Key Responsibilities
  • Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
  • Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
  • Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
  • Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
  • Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
  • Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX)
  • Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
  • Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
  • Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.
Required Qualifications
  • Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
  • Core Skills & Technical Expertise:
  • Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
  • Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
  • ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
  • MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
  • JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
  • Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
  • ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
  • MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
  • JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
  • Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
Preferred Skills
  • Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
  • Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
  • Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.

QFocus Technologies LLC is an Equal Employment Opportunity employer.

We are a group of passionate and experienced technology professionals working together with a singular focus to delight our customers by delivering quantifiable value and becoming a natural extension of your team!

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