As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. RESPONSIBILITIES:
As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. RESPONSIBILITIES:
Staff Package Design Engineer
Austin, TX · On-site +1
As the industry shifts toward heterogeneous integration, we are leading the charge in advanced packaging and are seeking a talented Staff Package Design Engineer to join our Advanced Silicon ...
Staff Package Design Engineer
Austin, TX · On-site +1
As the industry shifts toward heterogeneous integration, we are leading the charge in advanced packaging and are seeking a talented Staff Package Design Engineer to join our Advanced Silicon ...
Principal ASIC Package Design Engineer
$200K - $280K/yr
The Role We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM ...
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Principal ASIC Package Design Engineer
$200K - $280K/yr
The Role We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM ...
Sr. IC Package Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. RESPONSIBILITIES:
Sr. IC Package Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $225K/yr
As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. RESPONSIBILITIES:
Senior ASIC Package Design Engineer
Los Angeles, CA · On-site
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
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Senior ASIC Package Design Engineer
Los Angeles, CA · On-site
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
Senior ASIC Package Design Engineer
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
Senior ASIC Package Design Engineer
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
IC Package Engineer
Cupertino, CA · On-site
$2K/mo
IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...
... Engineering, Technology, Science, a related field, or equivalent practical experience. * 4 years of experience in chip package design/layout using Cadence allegro package designer (APD) or Mentor ...
... Engineering, Technology, Science, a related field, or equivalent practical experience. * 4 years of experience in chip package design/layout using Cadence allegro package designer (APD) or Mentor ...
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
Manager, Package Design Engineering
$230K - $265K/yr
Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of ...
Manager, Package Design Engineering
$230K - $265K/yr
Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of ...
Skills: As the IC Package Design Engineer, you demonstrate fundamental knowledge or proven experience in the following: * Proficient in Cadence APD & SiP. * Basic knowledge in high-speed IO ...
Skills: As the IC Package Design Engineer, you demonstrate fundamental knowledge or proven experience in the following: * Proficient in Cadence APD & SiP. * Basic knowledge in high-speed IO ...
Senior Engineer Package Designer
Bodega Bay, CA · On-site
$190K - $220K/yr
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
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Senior Engineer Package Designer
Bodega Bay, CA · On-site
$190K - $220K/yr
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of ...
Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of ...
We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic package and ...
We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic package and ...
Company Description We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic ...
Company Description We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic ...
We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic package and ...
Quick apply
We are currently searching for a Sr. Staff Package Design Engineer. RESPONSIBILITIES : * Design and develop hermetic/ceramic/metal and RAD (radiation) tolerant / class P plastic package and ...
Packaging Design Engineer I
Hayward, CA · On-site
$72K/yr
Packaging Design Engineer I is primarily responsible for developing custom packaging designs and ... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging ...
Packaging Design Engineer I
Hayward, CA · On-site
$72K/yr
Packaging Design Engineer I is primarily responsible for developing custom packaging designs and ... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging ...
Packaging Design Engineer I is primarily responsible for developing custom packaging designs and ... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging ...
Packaging Design Engineer I is primarily responsible for developing custom packaging designs and ... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging ...
Package Design Engineer information
See salary details
$90K - $94.2K
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$123.8K - $128K
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$128K - $132.3K
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$133.3K is the 25th percentile. Wages below this are outliers.
$132.3K - $136.5K
100% of jobs
$90K
$136.5K
How much do package design engineer jobs pay per year?
How does a Package Design Engineer typically collaborate with cross-functional teams during a product development cycle?
What is the difference between Package Design Engineer vs Packaging Designer?
| Aspect | Package Design Engineer | Packaging Designer |
|---|---|---|
| Credentials | Bachelor's in Packaging Engineering, Mechanical Engineering, or related fields | Bachelor's in Graphic Design, Industrial Design, or Packaging Design |
| Work Environment | Manufacturing facilities, R&D labs, engineering teams | Design studios, marketing departments, creative agencies |
| Industry Usage | Consumer goods, electronics, pharmaceuticals, food products | Consumer products, branding, marketing campaigns |
The Package Design Engineer focuses on developing functional, cost-effective, and manufacturable packaging solutions, often working closely with engineering teams. Packaging Designers primarily concentrate on the visual appeal, branding, and creative aspects of packaging. Both roles may collaborate, but their core responsibilities and skill sets differ significantly.
What are the key skills and qualifications needed to thrive as a Package Design Engineer, and why are they important?
What does a Package Design Engineer do?
Full-time
Posted 22 days ago
SpaceX rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
13th of 60 rated aerospace companies
Job description
SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems.
RESPONSIBILITIES:
- Own and drive advanced package selection, new product BGA configuration and package structure
- Responsible for package/SIP layout, optimization, design verification and tapeout
- Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
- Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
- Simulate and optimize signal/power integrity and RF performance of the package design
- Drive methodology, innovations, and productivity improvements in package design
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering, or physics
- 5+ years of experience with IC package design
PREFERRED SKILLS AND EXPERIENCE:
- Experience with Co-packaged Optics (CPO)
- Thorough understanding of signal and power integrity fundamentals
- Substrate design experience for RF, digital, high-speed and mixed signal die
- Experience with Cadence APD+/SIP or similar design tools
- Experience in package design electrical review, SI/PI analysis
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
- Experience in package design for manufacturing reviews
- Familiar with BGA package substrate technologies
- Strong problem solving skills with strong engineering fundamentals
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours or weekends as needed to meet mission critical deadlines
ITAR REQUIREMENTS:
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
About SpaceX
Sourced by ZipRecruiter
Industry
Accounting services
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US
Year founded
2002