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New Grad Asic Design Verification Engineer Jobs in Raleigh, NC

Apple Inc.

Design Verification Engineer

Cary, NC · On-site

$85 - $115/hr

A mindset to break the design is highly desirable. Furthermore, you will learn to develop verification plans for all features, implement these plans, support design bring‑up, DV environment ...

Hobbsnews

Principal ASIC Verification Engineer

Durham, NC · On-site

$153 - $352.50/hr

Our culture thrives on finding new and better ways to accelerate what's next. We know varied ... Determines architecture and logic design, design verification through software developed for ...

Nvidia

ASIC Design Efficiency Engineer

Durham, NC

We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary ... Execute and deliver fully verified, high performance, area and power efficient RTL to achieve ...

Microsoft

Formal Design Verification Engineer

Raleigh, NC · On-site

$132K/yr

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware ... We are looking for a Formal Design Verification Engineer to join the team. #SCHIE #CSME ...

Marvell

Principal Design Verification Engineer

Morrisville, NC · On-site

$127K - $155K/yr

  • Life

  • Retirement

... enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the ... verify that each design meets our customers' specifications whether they're a major telecom ...

Nvidia

Senior ASIC Design Engineer - GPU

Durham, NC · Hybrid

We are now looking for a Senior ASIC Engineer! NVIDIA is searching for an outstanding ASIC Engineer ... Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug ...

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in Raleigh, NC

New Grad Asic Design Verification Engineer information

See Raleigh, NC salary details

$102.6K

$145K

$162.3K

How much do new grad asic design verification engineer jobs pay per year?

As of Aug 17, 2026, the average yearly pay for new grad asic design verification engineer in Raleigh, NC is $144,986.00, according to ZipRecruiter salary data. Most workers in this role earn between $132,200.00 and $161,400.00 per year, depending on experience, location, and employer.

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

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For New Grad Asic Design Verification Engineer jobs in Raleigh, NC, the most frequently searched job titles are:

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New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in Raleigh, NC as of August 2026, with employment types broken down into 1% Internship, 84% Full Time, 10% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $144,986 per year, or $69.7 per hour.

Senior ASIC Verification Engineer

Hewlett Packard Enterprise Development LP

Durham, NC • On-site

Full-time

Re-posted 15 days ago

Job description

Senior ASIC Verification Engineer
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
This is a Hybrid role based in Durham, NC with an expectation that you'll be in the office 2 days per week. US Citizenship Preferred.
HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches.
Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.
As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow.
Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.
Position Summary
We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.
Key Responsibilities:
  • Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
  • Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
  • Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
  • Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
  • Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Required Skills and Qualifications:
  • 7+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
  • Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
  • Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
  • Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
  • Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred Skills and Experience:
  • Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
  • Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
  • Exposure to emulation environments, hardware acceleration, or traffic-model integration.
  • Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
  • Understanding of low-power (UPF) or formal verification methodologies.
  • Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
  • Experience with post-silicon bring-up and debug is a plus.
  • Familiarity with emulation environments and debug flows is desirable.

What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
#unitedstates
Job:
Engineering
Job Level:
TCP_04
"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 135,000 - 310,500 in North Carolina
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual's own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.

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