Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
Work on CAD tools development for the CPU/Fabric teams to improve efficiency Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers Push the frontiers of ...
Work on CAD tools development for the CPU/Fabric teams to improve efficiency Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers Push the frontiers of ...
Senior FPGA Engineer, Networking & Security
San Jose, CA · On-site
$184K - $208K/yr
Define the onboard networking architecture for Muon spacecraft, including switching, routing ... Design and build a spacecraft NoC (Network-on-Chip) and robust FPGA-to-FPGA links, with continuous ...
Senior FPGA Engineer, Networking & Security
San Jose, CA · On-site
$184K - $208K/yr
Define the onboard networking architecture for Muon spacecraft, including switching, routing ... Design and build a spacecraft NoC (Network-on-Chip) and robust FPGA-to-FPGA links, with continuous ...
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers * Push the frontiers of NoC/SoC tooling to enable productivity improvements * Understand the chip ...
System Performance Modeling Engineer
San Diego, CA · On-site
$106K - $145K/yr
This position is centered on system/platform architecture, with a strong emphasis on NoC (Network-on-Chip) topology architecture and system memory architecture (topologies, memory organization ...
System Performance Modeling Engineer
San Diego, CA · On-site
$106K - $145K/yr
This position is centered on system/platform architecture, with a strong emphasis on NoC (Network-on-Chip) topology architecture and system memory architecture (topologies, memory organization ...
SOC Platform Architect
San Diego, CA · On-site
$177K/yr
Create highly scalable SoC architecture in the area of Network-On-Chip, System MMU, Interrupts, Debug, Power Management & Security * Comprehend product requirements to steer generation of proper ...
SOC Platform Architect
San Diego, CA · On-site
$177K/yr
Create highly scalable SoC architecture in the area of Network-On-Chip, System MMU, Interrupts, Debug, Power Management & Security * Comprehend product requirements to steer generation of proper ...
Architect the register-access fabric with address decoding and access-protection logic. * Define ... Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC)
Architect the register-access fabric with address decoding and access-protection logic. * Define ... Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC)
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. * Consistent track record of efficiently implementing ...
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. * Consistent track record of efficiently implementing ...
SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, CA · On-site
$175K/yr
Network-on-Chip (NoC) design and integration * AXI, ACE, and APB interface design and verification * Queuing system design and implementation * Collaboration with architecture, IP, and physical ...
SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, CA · On-site
$175K/yr
Network-on-Chip (NoC) design and integration * AXI, ACE, and APB interface design and verification * Queuing system design and implementation * Collaboration with architecture, IP, and physical ...
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. Consistent track record of efficiently implementing ...
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. Consistent track record of efficiently implementing ...
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. * Consistent track record of efficiently implementing ...
Senior GPU Architect
Santa Clara, CA · On-site
$152K - $206K/yr
Experience with GPU architecture and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT. * Consistent track record of efficiently implementing ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Machine Learning SoC Architect
Sunnyvale, CA · On-site
$212K/yr
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
Machine Learning SoC Architect
Sunnyvale, CA · On-site
$212K/yr
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Senior GPU Memory Architect
Seattle, WA · On-site
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Senior GPU Memory Architect
Seattle, WA · On-site
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Machine Learning SoC Architect
Austin, TX · On-site
$212K/yr
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
Machine Learning SoC Architect
Austin, TX · On-site
$212K/yr
Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs * Identify ...
Senior GPU Memory Architect
Seattle, WA · On-site
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Senior GPU Memory Architect
Seattle, WA · On-site
An understanding in CPU or GPU architecture, memory systems, or network on-chip design. Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...
Network On Chip Architect information
See salary details
$21.15 - $27.75
0% of jobs
$27.75 - $34.35
0% of jobs
$34.35 - $40.95
0% of jobs
$40.95 - $47.55
2% of jobs
$47.55 - $54.15
6% of jobs
$54.15 - $60.75
13% of jobs
$62.30 is the 25th percentile. Wages below this are outliers.
$60.75 - $67.35
18% of jobs
The median wage is $71.62 / hr.
$67.35 - $73.95
18% of jobs
$73.95 - $80.55
18% of jobs
$81.10 is the 75th percentile. Wages above this are outliers.
$80.55 - $87.15
13% of jobs
$87.15 - $93.75
14% of jobs
$21
$71
$93
How much do network on chip architect jobs pay per hour?
As of Sep 11, 2026, the average hourly pay for network on chip architect in the United States is $71.96, according to ZipRecruiter salary data. Most workers in this role earn between $62.26 and $83.41 per hour, depending on experience, location, and employer.
What is the difference between Network On Chip Architect vs FPGA Designer?
| Aspect | Network On Chip Architect | FPGA Designer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of digital design | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related; FPGA design certifications beneficial |
| Work Environment | Design labs, hardware development teams, integrated circuit companies | Hardware design firms, semiconductor companies, research labs |
| Industry Usage | Integrated circuit design, SoC development, hardware architecture | FPGA development, prototyping, digital system design |
The Network On Chip Architect focuses on designing communication architectures within integrated circuits, while the FPGA Designer specializes in creating digital logic designs on FPGA platforms. Both roles require strong digital design skills and collaborate closely in hardware development, but their specific focus areas and tools differ significantly.
What are popular job titles related to Network On Chip Architect jobs?
For Network On Chip Architect jobs, the most frequently searched job titles are:
Senior CPU Tooling and Design Automation Engineer
Santa Clara, CA • On-site
Nvidia
• Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 8 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
Job description
NVIDIA is looking for a Senior CPU Tooling and Design Automation Engineer! Do you want to help drive the development of CPU technology for architectures used for artificial intelligence (AI) / deep learning (DL), high-performance computing (HPC), cloud service providers (CSP), gaming, virtual reality, and autonomous vehicles? Come join the CPU tooling and design automation team and help us push boundaries for all our CPU products!
What you'll be doing:
Work on CAD tools development for the CPU/Fabric teams to improve efficiency
Develop Network-on-Chip (NoC)/SoC tooling, working closely with architects, chip leads and designers
Push the frontiers of NoC/SoC tooling to enable productivity improvements
Understand the chip design flow and distill this knowledge into feature requirements for tooling
Develop complex automation involving advanced graph algorithms leading towards more push-button solutions
Work with teams throughout the company (Architects, RTL, PD etc.) on implementing cross-team solutions to achieve project targets
Drive cross-team methodologies for deployment of this tooling
What We Need To See:
Bachelor's degree in Computer Engineering or Electrical Engineering (or equivalent experience)
5+ years of relevant work experience in EDA tool development and developing flows
Proficiency with EDA style databases and basic graph algorithms
Experience with build flows such as Make and scripting languages
Experience deploying in-house EDA tools across groups, solving flow issues etc.
Strong interpersonal, communication and teamwork skills.
A drive to continuously learn and expand architectural breadth and depth
Ways to stand out from the crowd:
Background with Network-on-Chip tooling is a plus
Experience with netlist level tools is a plus
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US