San Francisco, CA · On-site
$76.25 - $102.25/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
San Francisco, CA · On-site
$76.25 - $102.25/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
Austin, TX · On-site
$64.25 - $86/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
Austin, TX · On-site
$64.25 - $86/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
Boston, MA · On-site
$70.25 - $94.25/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
Boston, MA · On-site
$70.25 - $94.25/hr
We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...
San Francisco, CA · On-site
Work hands-on with unreleased frontier models as part of how the chip gets built The role will ... Own architecture decisions for novel chip design end-to-end We offer competitive salary and equity.
San Francisco, CA · On-site
Work hands-on with unreleased frontier models as part of how the chip gets built The role will ... Own architecture decisions for novel chip design end-to-end We offer competitive salary and equity.
... network-on-chip and integration with other SoC models Running performance simulation of future ... architecture Communication and documentation skills Minimum Qualifications BS degree C ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... architecture Communication and documentation skills Minimum Qualifications BS degree C ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... architecture Communication and documentation skills Minimum Qualifications BS degree C ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... architecture Communication and documentation skills Minimum Qualifications BS degree C ...
C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC ... Coursework and/or experience in computer architecture and the HW/SW stack * Coursework and/or ...
C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC ... Coursework and/or experience in computer architecture and the HW/SW stack * Coursework and/or ...
Cupertino, CA · On-site
$150K - $225K/yr
C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC ... Coursework and/or experience in computer architecture and the HW/SW stack * Coursework and/or ...
Cupertino, CA · On-site
$150K - $225K/yr
C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC ... Coursework and/or experience in computer architecture and the HW/SW stack * Coursework and/or ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... on-chip architecture and design is a big plus Ability to study a problem in depth, design ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... on-chip architecture and design is a big plus Ability to study a problem in depth, design ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... on-chip architecture and design is a big plus Ability to study a problem in depth, design ...
... network-on-chip and integration with other SoC models Running performance simulation of future ... on-chip architecture and design is a big plus Ability to study a problem in depth, design ...
... network-on-chip architecture and design is a big plus Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture ...
... network-on-chip architecture and design is a big plus Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture ...
... network-on-chip architecture and design Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture Communication and ...
... network-on-chip architecture and design Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture Communication and ...
... network-on-chip architecture and design Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture Communication and ...
... network-on-chip architecture and design Ability to study a problem in depth, design experiments, analyze data, and present results Experience with Cellular/5G modem architecture Communication and ...
San Jose, CA · On-site
$209K - $299K/yr
Develop logic design, RTL coding, and simulation for Network on Chip IPs and other FPGA IPs/subsystems for integration into full chip designs. * Participate in defining the architecture and ...
San Jose, CA · On-site
$209K - $299K/yr
Develop logic design, RTL coding, and simulation for Network on Chip IPs and other FPGA IPs/subsystems for integration into full chip designs. * Participate in defining the architecture and ...
Irvine, CA · On-site
$100 - $125/hr
Familiarity with processor architecture, memory and cache subsystems, on-chip interconnects and network-on-chip technology * Familiarity with either UVM based verification flow or RTL to GDS design ...
New
Irvine, CA · On-site
$100 - $125/hr
Familiarity with processor architecture, memory and cache subsystems, on-chip interconnects and network-on-chip technology * Familiarity with either UVM based verification flow or RTL to GDS design ...
New
... Network-on-Chip/NoC, and security enclaves). * PPA Optimization: Conduct rigorous Power ... Write detailed architecture specifications and serve as the technical lead during the RTL ...
... Network-on-Chip/NoC, and security enclaves). * PPA Optimization: Conduct rigorous Power ... Write detailed architecture specifications and serve as the technical lead during the RTL ...
$100K/yr
Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis. Why Architect You'll join a founding team building the future of ...
$100K/yr
Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis. Why Architect You'll join a founding team building the future of ...
San Jose, CA · On-site
$209K - $299K/yr
You will work closely with architecture, design, verification, software, physical design, and ... Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip ...
San Jose, CA · On-site
$209K - $299K/yr
You will work closely with architecture, design, verification, software, physical design, and ... Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip ...
Austin, TX · On-site
You will work with the XPU/Compute chip architect and the memory architect to synthesize the final ... Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs ...
Austin, TX · On-site
You will work with the XPU/Compute chip architect and the memory architect to synthesize the final ... Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs ...
Palo Alto, CA · On-site
$160K/yr
Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis. Why Architect You'll join a founding team building the future of ...
Palo Alto, CA · On-site
$160K/yr
Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis. Why Architect You'll join a founding team building the future of ...
$21.15 - $27.75
0% of jobs
$27.75 - $34.35
0% of jobs
$34.35 - $40.95
0% of jobs
$40.95 - $47.55
2% of jobs
$47.55 - $54.15
6% of jobs
$54.15 - $60.75
13% of jobs
$62.30 is the 25th percentile. Wages below this are outliers.
$60.75 - $67.35
18% of jobs
The median wage is $71.62 / hr.
$67.35 - $73.95
18% of jobs
$73.95 - $80.55
18% of jobs
$81.10 is the 75th percentile. Wages above this are outliers.
$80.55 - $87.15
13% of jobs
$87.15 - $93.75
14% of jobs
$21
$71
$93
| Aspect | Network On Chip Architect | FPGA Designer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of digital design | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related; FPGA design certifications beneficial |
| Work Environment | Design labs, hardware development teams, integrated circuit companies | Hardware design firms, semiconductor companies, research labs |
| Industry Usage | Integrated circuit design, SoC development, hardware architecture | FPGA development, prototyping, digital system design |
The Network On Chip Architect focuses on designing communication architectures within integrated circuits, while the FPGA Designer specializes in creating digital logic designs on FPGA platforms. Both roles require strong digital design skills and collaborate closely in hardware development, but their specific focus areas and tools differ significantly.
For Network On Chip Architect jobs, the most frequently searched job titles are:
San Francisco, CA • On-site
$76.25 - $102.25/hr
Other
Re-posted yesterday
We’re looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system.
Ideal Background:
Nice to Have:
