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Mixed Signal Verification Jobs (NOW HIRING)

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$171.60K - $302.20K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$120.30K - $210.10K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$171.60K - $302.20K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$120.30K - $210.10K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160.20K - $195.60K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160.20K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

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How much do mixed signal verification jobs pay per hour?

As of May 29, 2026, the average hourly pay for mixed signal verification in the United States is $20.70, according to ZipRecruiter salary data. Most workers in this role earn between $15.38 and $21.88 per hour, depending on experience, location, and employer.

What is a Mixed Signal Verification job?

A Mixed Signal Verification job involves testing and validating the functionality of integrated circuits that include both analog and digital components. Engineers in this role develop verification environments, create testbenches, and use methodologies like UVM or custom analog verification techniques to ensure circuit performance. They work with simulation tools such as SPICE, Verilog-AMS, or SystemVerilog to verify signal integrity, timing, and functionality. The goal is to detect and resolve design issues before fabrication, ensuring reliable and high-performance chips.

What are the key skills and qualifications needed to thrive in the Mixed Signal Verification position, and why are they important?

To thrive as a Mixed Signal Verification engineer, you need strong knowledge of analog and digital circuit design, verification methodologies, and a relevant degree in electrical or electronics engineering. Familiarity with verification tools such as UVM, SystemVerilog, SPICE simulators, and waveform analysis software is crucial, and industry certifications can be valuable. Excellent problem-solving abilities, attention to detail, and effective communication skills help you collaborate efficiently and report findings clearly. These competencies are essential for ensuring the reliability and performance of complex mixed-signal integrated circuits in product development.

What are some typical challenges faced by a Mixed Signal Verification engineer and how is support provided within teams?

Mixed Signal Verification engineers often encounter challenges in accurately modeling and validating the interactions between analog and digital circuit components, which can be intricate and require in-depth simulation. Team support typically includes close collaboration with both design engineers and other verification specialists, frequent design reviews, and shared troubleshooting resources. Many companies provide mentorship programs and encourage knowledge-sharing sessions to help address technical issues. This collaborative environment ensures engineers have the guidance and tools needed to address complex verification tasks and continually enhance their expertise.
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Mixed Signal Verification jobs near you
Infographic showing various Mixed Signal Verification job openings in the United States as of May 2026, with employment types broken down into 67% Full Time, and 33% Contract. Highlights an 100% In-person job distribution, with an average salary of $43,051 per year, or $20.7 per hour.

Mixed-Signal Verification Engineer

Chelsea Search Group

Allen, TX • On-site

$126.50K/yr

Full-time

Posted 15 days ago

Job description

We are seeking a highly motivated Mixed-Signal Verification Engineer III to support verification of analog and mixed-signal IP integrated within digital-on-top SoC environments. Reporting to the Analog Design Team Manager, this individual contributor role will lead development and execution of verification strategies for complex power, clocking, and mixed-signal subsystems prior to tape-out. The ideal candidate brings strong expertise in SystemVerilog, UVM methodologies, and behavioral modeling, along with hands-on experience verifying analog IP in large-scale SoC environments.
Key Responsibilities
• Lead mixed-signal verification activities for analog IP blocks using SystemVerilog and UVM-based methodologies.
• Develop scalable digital-on-top verification environments and testbenches incorporating behavioral models for analog IP including PLLs, LDOs, oscillators, DC/DC converters, and related circuitry.
• Translate analog and mixed-signal specifications into comprehensive verification plans, assertions, coverage models, and checkers.
• Create and maintain behavioral models using SystemVerilog real-number modeling (RNM) and/or Verilog-AMS for efficient system-level simulation.
• Execute regression testing, analyze failures, and debug issues across analog, digital, and mixed-signal domains.
• Verify configuration, calibration, monitoring, protection, and fault-handling interfaces between analog IP and digital control logic.
• Collaborate closely with analog designers, digital verification engineers, and system architects to ensure verification completeness and tape-out readiness.
Behavioral Modeling & Abstraction
• Develop high-level functional and behavioral models optimized for large-scale SoC simulation while maintaining key analog performance characteristics.
• Define modeling assumptions, validation approaches, and abstraction strategies in partnership with analog design teams.
• Contribute to mixed-signal co-simulation methodologies balancing simulation accuracy, runtime efficiency, and model reuse.
Tools, Methodologies & Quality
• Utilize industry-standard digital, mixed-signal, and AMS simulation and verification tools.
• Apply coverage-driven and assertion-based verification methodologies to ensure robust design validation.
• Participate in design and verification reviews while adhering to established regression, version control, and documentation practices.
• Identify and implement opportunities for workflow automation and verification flow improvements.
Collaboration & Technical Leadership
• Work independently on complex verification assignments while providing mentorship to junior engineers.
• Contribute verification expertise during IP architecture, integration, and design reviews.
• Proactively identify technical risks, communicate issues effectively, and drive resolution across cross-functional teams.
Minimum Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or a related technical discipline.
• 6+ years of experience in mixed-signal and/or digital IC verification.
• Strong proficiency with SystemVerilog and UVM-based verification methodologies.
• Hands-on experience developing behavioral models using Verilog-AMS and/or SystemVerilog real-number modeling.
• Experience verifying analog and mixed-signal IP within digital-on-top SoC environments.
Preferred Qualifications
• Familiarity with power management and clocking architectures including bandgaps, PLLs, LDOs, oscillators, and DC/DC converters.
• Experience with coverage-driven verification, assertions, and formal verification concepts.
• Exposure to automotive, industrial, or safety-critical semiconductor development environments.
• Experience with scripting, automation, or AI-assisted verification workflows.