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Trainee Mixed Signal Verification Jobs (NOW HIRING)

Retym

Mixed Signal Verification Engineer

Austin, TX · On-site

$134K/yr

Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. * Create behavioural models for analog blocks in accordance with ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$122K - $214K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$175K - $308K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$175K - $308K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$122K - $214K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

K2 Space

OR

$160K - $230K/yr

The Role We are seeking a Senior Mixed-Signal Verification Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of ...

K2 Space

Senior Mixed-Signal Verification Engineer

$160K - $230K/yr

The Role We are seeking a Senior Mixed-Signal Verification Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of ...

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How much do trainee mixed signal verification jobs pay per hour?

As of Jul 14, 2026, the average hourly pay for trainee mixed signal verification in the United States is $17.24, according to ZipRecruiter salary data. Most workers in this role earn between $12.74 and $18.27 per hour, depending on experience, location, and employer.
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Trainee Mixed Signal Verification jobs near you

Mixed Signal Verification Engineer

Retym

Austin, TX • On-site

$134K/yr

Full-time

Re-posted 27 days ago

Job description

Description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer.
Requirements
Key Responsibilities:
  • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
  • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
  • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
  • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
  • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.

Minimum Qualifications
  • 5+ years of experience
  • Experience in Behavioural Modelling (BM) of Analog design for digital verification
  • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
  • Experience in Verilog/SystemVerilog coding
  • Experience in Virtuoso Schematics tools
  • Basic knowledge in Analog design

Preferred Qualifications
  • Experience in UVM
  • Experience in both Synopsys and Cadence tools is an advantage

Additional Skills
  • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
  • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
  • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

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