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Lvs Physical Verification Engineer Jobs (NOW HIRING)

Intel Corporation

Physical Verification Engineer

Phoenix, AZ · On-site

$135K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC ...

Intel

Physical Verification Engineer

Phoenix, AZ · On-site

$135K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC ...

Intel

Physical Verification Engineer

Hillsboro, OR · On-site

$148K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC ...

Intel

Physical Verification Engineer

Santa Clara, CA · On-site

$159K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC ...

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Lvs Physical Verification Engineer information

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$95K

$141.5K

How much do lvs physical verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for lvs physical verification engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Lvs Physical Verification Engineer vs Physical Design Engineer?

AspectLvs Physical Verification EngineerPhysical Design Engineer
Primary RoleVerifies physical layouts for LVS (Layout vs. Schematic) complianceDesigns and implements physical chip layouts
Skills & CertificationsKnowledge of LVS tools, verification processes, EDA toolsExperience with physical design tools, STA, DRC/LVS checks
Work EnvironmentIC design verification teams, EDA tool usagePhysical implementation teams, chip layout design
Industry UsageCommon in semiconductor verification workflowsCommon in chip design and physical implementation

While both roles are integral to IC design, the Lvs Physical Verification Engineer focuses on verifying that physical layouts match schematic designs, ensuring LVS compliance. In contrast, the Physical Design Engineer is responsible for creating and optimizing the physical layout itself. Both roles require familiarity with EDA tools and semiconductor industry standards, but they serve different stages in the chip development process.

What are popular job titles related to Lvs Physical Verification Engineer jobs?

For Lvs Physical Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Lvs Physical Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 74% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Principal Physical Verification Engineer

Irvine, CA • On-site

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$150K - $250K/yr

Other

Posted 27 days ago

Job description

Principal Physical Verification Engineer

  • Irvine, CA


Principal Full-Chip Physical Verification Engineer
Key Responsibilities
Team & Project Leadership

  • Lead full chip Physical Verification effort

  • Own execution plans, schedules for full-chip

  • Drive accountability for quality, milestones, and tapeout readiness.

  • Conduct full chip and blocks PV checks


Physical Verification Ownership

  • Ownership of full chip verification

  • Work with internal analog team to ensure clean IP delivery

  • Responsible for running and analyzing DRC/ERC/LUP/PERC results

  • Experience with using either ICV or Calibre verification tools

  • Understanding advance TSMC DRC rules


Cross-Functional Collaboration

  • Partner with analog, block, chip top owners to ensure clean floorplan

  • Provide early guidance on corner case requirements

  • Influence floorplan constraints, hierarchy, and implementation strategy

  • Participate in tapeout readiness reviews


Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering or related field.

  • 7+ years of experience with full-chip verifications


Proven hands-on experience with:

  • Physical Verification tool (ICV/Calibre)

  • Able to assemble a flow to support block/chip level PV


Strong expertise in:

  • Floorplanning to avoid DRC/LVS issues

  • Provide guidance to analog IP team to allow for clean integration


Preferred Qualifications

  • Experience in advanced technology nodes (7nm, 5nm, 3nm)

  • Automation skills using Tcl, Python, or shell scripting


Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)


Javier Leon
Talent Acquisition
619-227-3193 cell/text
javier.leon@celero.inc
www.celero.inc

#J-18808-Ljbffr

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