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Cad Physical Verification Engineer Jobs (NOW HIRING)

TetraMem, Inc.

CAD Engineer

San Jose, CA · On-site

$110K - $250K/yr

... CAD engineering, with at least 2 years of experience in ... Strong knowledge of analog design, custom layout and physical verification flows * Familiar with ...

Apple

SoC Physical Design Engineer - Power Delivery

Austin, TX · On-site

$134K - $138K/yr

Ability to work multi-functionally with CAD/Physical Verification/Electrical analysis and PnR teams ... programming skills, including the ability to write maintainable and reusable scripts/programs of ...

OMNIVISION

Analog CAD Engineer

Santa Clara, CA

$110K - $145K/yr

Support and enhance the Analog CAD design flow across the full custom IC design cycle, including schematic, layout, simulation, and physical verification using Cadence Virtuoso and Calibre tools.

OMNIVISION

Analog CAD Engineer

Santa Clara, CA · On-site

$110K - $145K/yr

Support and enhance the Analog CAD design flow across the full custom IC design cycle, including schematic, layout, simulation, and physical verification using Cadence Virtuoso and Calibre tools.

Apple

Physical Design Methodology CAD Engineer

Austin, TX · On-site

$134K - $138K/yr

... of CAD algorithms and ML. We are looking for passionate engineers to join our team. In this role ... Expertise in analysis aspects of Physical Design - extraction, timing, noise, physical verification ...

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

Support physical verification activities including DRC, LVS, and related sign-off checks and help resolve identified issues. * Work with RTL, architecture, DFT, CAD/EDA, and other engineering teams ...

Micron Technology, Inc

Staff Engineer, CE CAD

Boise, ID · On-site

$98K - $312K/yr

Experience with custom memory design, including DDR, LPDDR, HBM, or NAND, physical verification ... Job Profile(s): CAD Engineer 3 - CAD MTS Relocation Level: TBD Full-Time Salary Information The US ...

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Cad Physical Verification Engineer information

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$44K

$93.1K

$151K

How much do cad physical verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for cad physical verification engineer in the United States is $93,130.00, according to ZipRecruiter salary data. Most workers in this role earn between $70,000.00 and $119,500.00 per year, depending on experience, location, and employer.

What is a CAD Physical Verification Engineer?

Cad Physical Verification Engineers are specialists who use Computer-Aided Design (CAD) tools to verify that integrated circuit (IC) layouts comply with design rules and manufacturing requirements. They perform checks such as Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checking (ERC) to ensure the physical design matches the intended circuit and can be reliably manufactured. Their work is crucial for identifying and correcting potential errors before fabrication, reducing costly rework and improving chip yield.

What are some common challenges faced by a CAD Physical Verification Engineer during the tapeout phase?

During the tapeout phase, CAD Physical Verification Engineers often encounter challenges such as tight deadlines, last-minute design changes, and the need to resolve complex design rule violations quickly. Ensuring that the physical layout meets all foundry requirements while coordinating with design, layout, and process teams can be demanding. Effective communication, strong problem-solving skills, and attention to detail are essential for successfully navigating this critical stage and ensuring a smooth handoff to manufacturing.

What are the key skills and qualifications needed to thrive as a CAD Physical Verification Engineer, and why are they important?

To thrive as a CAD Physical Verification Engineer, you need a strong background in semiconductor physics, VLSI design, and a relevant engineering degree. Proficiency in EDA tools such as Calibre or Hercules, scripting languages like Python or Perl, and familiarity with DRC/LVS verification flows are essential. Attention to detail, problem-solving abilities, and strong communication skills distinguish top performers in this role. These skills and qualifications are crucial for ensuring that integrated circuit designs meet stringent manufacturing and quality standards.

What is the difference between Cad Physical Verification Engineer vs Cad Design Engineer?

AspectCad Physical Verification EngineerCad Design Engineer
CredentialsTypically requires a degree in electronics, VLSI, or related fields; certifications in EDA tools are commonRequires a degree in electronics, electrical engineering, or VLSI design; certifications in CAD tools are beneficial
Work EnvironmentWorks in EDA tool environments, verifying physical layouts against design rulesDesigns circuit layouts, schematics, and system architecture using CAD software
Industry UsageUsed in semiconductor and chip manufacturing companiesUsed across semiconductor, electronics, and integrated circuit industries

The Cad Physical Verification Engineer focuses on ensuring that chip layouts meet manufacturing rules, while the Cad Design Engineer is responsible for creating the initial circuit and layout designs. Both roles require familiarity with CAD tools and work within the semiconductor industry, but their core tasks differ significantly.

What are popular job titles related to Cad Physical Verification Engineer jobs?

For Cad Physical Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Cad Physical Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 74% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $93,130 per year, or $44.8 per hour.

CAD Engineer

San Jose, CA • On-site

TetraMem, Inc.
Computer and Peripheral Equipment Manufacturing • 11 - 50 employees
Learn more about TetraMem, Inc.external

$110K - $250K/yr

Full-time

Re-posted yesterday

Job description

Responsibilities:
  • Development of in-house CAD tools for analog design, analog layout, database management, digital frontend and backend, SoC sign-off
  • Automation in design and verification flow using languages such as tcl, skill, or python
  • Collaborate with design engineer, verification engineer, IT, and EDA vendor to optimize EDA license usage
  • Drive innovation by researching and implementing advanced CAD methodologies that either increase productivity or reduce EDA cost
  • Mentor and provide technical guidance to junior engineers, fostering a culture of continuous learning and professional development.
  • Participate in design reviews, provide constructive feedback, and contribute to the improvement of design processes and standards.

Requirements:
  • Degree in Electrical Engineering or Computer Engineering, with experience in analog or digital IC design flow and CAD methodology.
  • 10+ years of experience in CAD engineering, with at least 2 years of experience in <28nm technology node EDA methodology
  • Strong knowledge of analog design, custom layout and physical verification flows
  • Familiar with common EDA environment tools (e.g., Synopsys, Cadence, Siemens etc.), include licensing, environment setup, automation API, and have working knowledge on tool usage
  • Experience with at least one of SKILL or TCL
  • Proficient with UNIX based operating system, file management, disk management and security
  • Ability to automate design methodologies and create productivity scripts with design engineers
  • Ability to work in a startup environment and to work both independently and as a team player

The following skillsets will be considered a strong asset:
  • Experience with circuit or layout design in Cadence environment
  • Experience with ASIC design in Synopsys environment

Salary Range: $110,000 - $250,000 / year

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