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Principal Physical Verification Engineer Jobs (NOW HIRING)

Intel

Physical Verification Engineer

Hillsboro, OR

$148K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Intel

Physical Verification Engineer

Phoenix, AZ

$135K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Intel

Physical Verification Engineer

Santa Clara, CA

$159K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Micron

SoC Physical Verification Engineer, HBM

Folsom, CA · On-site

$97K - $205K/yr

As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality ...

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How much do principal physical verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for principal physical verification engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

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Principal Physical Verification Engineer

Irvine, CA • On-site

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$150K - $250K/yr

Other

Posted 26 days ago

Job description

Principal Physical Verification Engineer

  • Irvine, CA


Principal Full-Chip Physical Verification Engineer
Key Responsibilities
Team & Project Leadership

  • Lead full chip Physical Verification effort

  • Own execution plans, schedules for full-chip

  • Drive accountability for quality, milestones, and tapeout readiness.

  • Conduct full chip and blocks PV checks


Physical Verification Ownership

  • Ownership of full chip verification

  • Work with internal analog team to ensure clean IP delivery

  • Responsible for running and analyzing DRC/ERC/LUP/PERC results

  • Experience with using either ICV or Calibre verification tools

  • Understanding advance TSMC DRC rules


Cross-Functional Collaboration

  • Partner with analog, block, chip top owners to ensure clean floorplan

  • Provide early guidance on corner case requirements

  • Influence floorplan constraints, hierarchy, and implementation strategy

  • Participate in tapeout readiness reviews


Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering or related field.

  • 7+ years of experience with full-chip verifications


Proven hands-on experience with:

  • Physical Verification tool (ICV/Calibre)

  • Able to assemble a flow to support block/chip level PV


Strong expertise in:

  • Floorplanning to avoid DRC/LVS issues

  • Provide guidance to analog IP team to allow for clean integration


Preferred Qualifications

  • Experience in advanced technology nodes (7nm, 5nm, 3nm)

  • Automation skills using Tcl, Python, or shell scripting


Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)


Javier Leon
Talent Acquisition
619-227-3193 cell/text
javier.leon@celero.inc
www.celero.inc

#J-18808-Ljbffr

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