DV Intern
San Jose, CA ยท On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with high-speed digital logic * Exposure to ASIC or SoC design concepts * Familiarity ...
Quick apply
San Jose, CA ยท On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with high-speed digital logic * Exposure to ASIC or SoC design concepts * Familiarity ...
Quick apply
San Jose, CA ยท On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with high-speed digital logic * Exposure to ASIC or SoC design concepts * Familiarity ...
Austin, TX ยท On-site
$134K - $164K/yr
The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT ... logic design, and exposure to DFT is a plus
Austin, TX ยท On-site
$134K - $164K/yr
The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT ... logic design, and exposure to DFT is a plus
Hillsboro, OR ยท Hybrid
$127K - $236K/yr
The successful candidate will participate in pre-silicon RTL Verification activities related to ... System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing ...
Hillsboro, OR ยท Hybrid
$127K - $236K/yr
The successful candidate will participate in pre-silicon RTL Verification activities related to ... System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
Hillsboro, OR ยท On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Work with verification team on regression failure debug and root cause, and provide RTL fix if ...
Hillsboro, OR ยท On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Work with verification team on regression failure debug and root cause, and provide RTL fix if ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
Austin, TX ยท On-site
$134K - $164K/yr
Job Title, Lab: Contractor Verification Engineer, APL General Description Vision: Perform pre ... Understanding of micro-architecture and logic design fundamentals, e.g. finite state machines ...
Austin, TX ยท On-site
$134K - $164K/yr
Job Title, Lab: Contractor Verification Engineer, APL General Description Vision: Perform pre ... Understanding of micro-architecture and logic design fundamentals, e.g. finite state machines ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
Hillsboro, OR ยท On-site
Principal Logic Design Engineer Position Description: Protingent Staffing has an exciting Direct ... Collaborate closely with verification team to shape test plans and improve verification coverage
Hillsboro, OR ยท On-site
Principal Logic Design Engineer Position Description: Protingent Staffing has an exciting Direct ... Collaborate closely with verification team to shape test plans and improve verification coverage
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...
Austin, TX ยท On-site
$100 - $125/hr
The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT ... Good knowledge of general logic design, and exposure to DFT is a plus Apple is an equal opportunity ...
Austin, TX ยท On-site
$100 - $125/hr
The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT ... Good knowledge of general logic design, and exposure to DFT is a plus Apple is an equal opportunity ...
Rancho Cordova, CA ยท On-site
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...
Quick apply
Rancho Cordova, CA ยท On-site
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...
Chandler, AZ ยท On-site
$133K - $163K/yr
Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...
Chandler, AZ ยท On-site
$133K - $163K/yr
Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...
Chandler, AZ ยท On-site
$133K - $163K/yr
Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...
Chandler, AZ ยท On-site
$133K - $163K/yr
Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...
Rancho Cordova, CA ยท On-site
$105K - $164K/yr
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...
Rancho Cordova, CA ยท On-site
$105K - $164K/yr
Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture, and microarchitecture Should be a great teammate with excellent communication skills and be able to work independently on the verification efforts for a block/area of ...
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture, and microarchitecture Should be a great teammate with excellent communication skills and be able to work independently on the verification efforts for a block/area of ...
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture, and microarchitecture Experience with developing testplans ... verification efforts for a block/area of the design
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture, and microarchitecture Experience with developing testplans ... verification efforts for a block/area of the design
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture and microarchitecture Programming experience in at least one of the following languages: C, C++, or SystemVerilog Experience with at least one of the following ...
Austin, TX ยท On-site
$134K - $164K/yr
... logic design, chip architecture and microarchitecture Programming experience in at least one of the following languages: C, C++, or SystemVerilog Experience with at least one of the following ...
Beaverton, OR ยท On-site
$141K - $172K/yr
... logic design, chip architecture and microarchitecture Programming experience in C/C++ or ... verification efforts for a block/area of the design
Beaverton, OR ยท On-site
$141K - $172K/yr
... logic design, chip architecture and microarchitecture Programming experience in C/C++ or ... verification efforts for a block/area of the design
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
For Logic Design Verification Intern jobs, the most frequently searched job titles are:

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
UVM or formal verification experience
Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.