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Logic Design Verification Intern Jobs (NOW HIRING)

DV Intern

San Jose, CA ยท On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with high-speed digital logic * Exposure to ASIC or SoC design concepts * Familiarity ...

The successful candidate will participate in pre-silicon RTL Verification activities related to ... System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing ...

PE Logic Design

Hillsboro, OR ยท On-site

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Work with verification team on regression failure debug and root cause, and provide RTL fix if ...

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT ... Good knowledge of general logic design, and exposure to DFT is a plus Apple is an equal opportunity ...

Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...

Staff Design Verification Engineer

Chandler, AZ ยท On-site

$133K - $163K/yr

Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...

Senior Design Verification Engineer

Chandler, AZ ยท On-site

$133K - $163K/yr

Cirrus Logic is also known for its award-winning culture, which was built on a foundation of ... We are seeking an experienced and innovative Design Verification Engineer to join a world-class ...

IP Logic Design Engineer

Rancho Cordova, CA ยท On-site

$105K - $164K/yr

Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components * Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with ...

CPU Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

... logic design, chip architecture, and microarchitecture Should be a great teammate with excellent communication skills and be able to work independently on the verification efforts for a block/area of ...

CPU Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

... logic design, chip architecture, and microarchitecture Experience with developing testplans ... verification efforts for a block/area of the design

CPU Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

... logic design, chip architecture and microarchitecture Programming experience in at least one of the following languages: C, C++, or SystemVerilog Experience with at least one of the following ...

Showing results 41-60

Logic Design Verification Intern information

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How much do logic design verification intern jobs pay per hour?

As of Sep 9, 2026, the average hourly pay for logic design verification intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are popular job titles related to Logic Design Verification Intern jobs?

For Logic Design Verification Intern jobs, the most frequently searched job titles are:

Infographic showing various Logic Design Verification Intern job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

DV Intern

San Jose, CA โ€ข On-site

Other

Re-posted 4 days ago


Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

  • Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.

  • Familiarity with high-speed digital logic

  • Exposure to ASIC or SoC design concepts

  • Familiarity with SystemVerilog, UVM, or Python

  • Familiarity with verification work and writing test benches

  • Familiarity with physical design flows and tooling

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • UVM or formal verification experience

  • ​Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

  • 12-week paid internship

  • Generous housing support for those relocating

  • Daily lunch and dinner in our office

  • Based at our office in San Jose, CA

  • Direct mentorship from industry leaders and world-class engineers

  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

 

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.