ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both ...
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RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both ...
You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ... Experience mentoring junior engineers and leading design teams * Strong technical writing skills ...
You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple ... Experience mentoring junior engineers and leading design teams * Strong technical writing skills ...
ASIC/SoC Design Engineer, RTL design for SoC IPs
San Jose, CA · On-site
$145.60K/yr
... junior engineers while driving projects to successful completion. KEY RESPONSIBILITIES: * RTL ... Drive design from concept through production silicon across all phases: specification, RTL coding ...
ASIC/SoC Design Engineer, RTL design for SoC IPs
San Jose, CA · On-site
$145.60K/yr
... junior engineers while driving projects to successful completion. KEY RESPONSIBILITIES: * RTL ... Drive design from concept through production silicon across all phases: specification, RTL coding ...
RTL Design Engineer
San Diego, CA · On-site
... RTL design and test planning - Timing closure experience including timing constraints and PTSI. - Prior experience in digital and mixed signal circuit design for high speed PHYs - Hands-on experience ...
RTL Design Engineer
San Diego, CA · On-site
... RTL design and test planning - Timing closure experience including timing constraints and PTSI. - Prior experience in digital and mixed signal circuit design for high speed PHYs - Hands-on experience ...
The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with ...
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The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with ...
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
Power Engineer (RTL Design) Work Location: Sunnyvale, CA/ Austin, TX (Onsite) Job Overview We are looking for: * Design Engineers with power analysis experience * Verification Engineers with power ...
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
Power Engineer (RTL Design) Work Location: Sunnyvale, CA/ Austin, TX (Onsite) Job Overview We are looking for: * Design Engineers with power analysis experience * Verification Engineers with power ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
SerDes RTL Design Engineer
San Jose, CA · On-site
$145.60K/yr
AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. THE ...
SerDes RTL Design Engineer
San Jose, CA · On-site
$145.60K/yr
AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. THE ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
Engineer, GPU RTL Design - Pixel Pipe
San Jose, CA · On-site
$116K - $174K/yr
Role and Responsibilities As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
... design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
FPGA RTL Design and Board Validation
Santa Clarita, CA · On-site
$124.80K - $172K/yr
Semiconductor We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal ...
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FPGA RTL Design and Board Validation
Santa Clarita, CA · On-site
$124.80K - $172K/yr
Semiconductor We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal ...
PHY RTL Design Engineer
$120.30K - $210.10K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120.30K - $210.10K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
Junior Rtl Design Engineer information
See California salary details
$33.1K - $39.9K
3% of jobs
$39.9K - $46.7K
20% of jobs
$48.2K is the 25th percentile. Wages below this are outliers.
$46.7K - $53.5K
7% of jobs
$53.5K - $60.3K
6% of jobs
$60.3K - $67.2K
12% of jobs
The median wage is $67.6K / yr.
$67.2K - $74K
17% of jobs
$77.6K is the 75th percentile. Wages above this are outliers.
$74K - $80.8K
17% of jobs
$80.8K - $87.6K
7% of jobs
$87.6K - $94.4K
4% of jobs
$94.4K - $101.2K
3% of jobs
$101.2K - $108.1K
2% of jobs
$33.1K
$70.9K
$108.1K
How much do junior rtl design engineer jobs pay per year?
As of May 30, 2026, the average yearly pay for junior rtl design engineer in California is $70,859.00, according to ZipRecruiter salary data. Most workers in this role earn between $47,900.00 and $79,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?
To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.
What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?
Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are Junior RTL Design Engineers?
Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.
What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Junior Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related field; some certifications | Bachelor's or higher in Electrical/Electronic Engineering; certifications vary |
| Work Environment | Design teams in semiconductor or electronics companies | Design and development teams in similar industries |
| Employer & Industry Usage | Commonly employed in chip design, FPGA, ASIC development | Used in digital circuit and system design across industries |
Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.
What are popular job titles related to Junior Rtl Design Engineer jobs in California? For Junior Rtl Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Junior Rtl Design Engineer jobs in California look for? The top searched job categories for Junior Rtl Design Engineer jobs in California are:
What cities in California are hiring for Junior Rtl Design Engineer jobs? Cities in California with the most Junior Rtl Design Engineer job openings:
Job description
Title: ASIC/SoC RTL Design Engineer
Location: Palo Alto, CA (Or potentially Burlington, MA)
Length of Contract: 6 months+ (Temp-to-Perm)
Ideal Start: 6/1/2026
Responsibilities :
Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
Must haves:
- 8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
- Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
- Proven experience owning subsystems from architecture RTL tapeout
- Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
- Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
- Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)
Pluses:
- Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
- Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
- Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
About Oxford Global Resources
Sourced by ZipRecruiter
Oxford Global Resources delivers tailored solutions for any technical challenges you face using our partnership-first approach. We specialize in workforce mobilization, digital transformation, and modern enterprise. We are committed to providing you with The Right Talent. Right Now. In 1984, we started Oxford with a handful of employees in a converted schoolhouse in Reading, Massachusetts. The people that shape our organization are some of the best in the industry. They are dedicated to making an impact and are with you every step of the way. We strive to meet the most pressing needs, solve the most complex problems, and go beyond expectations for our clients and our consultants. Together, we drive great outcomes. Whether you’d like to join the thousands of professionals who trust Oxford to advance their careers or partner with us to solve a challenge your business is facing, contact us at any of our 35 global offices.
Industry
Recruiting and staffing services
Company size
501 - 1,000 Employees
Headquarters location
Beverly, MA, US
Year founded
1984