PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a ...
Quick apply
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a ...
Quick apply
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a ...
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a ...
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a ...
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
Quick apply
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
Quick apply
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
San Jose, CA · On-site
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
San Jose, CA · On-site
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
$35 - $45/hr
RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. * Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and ...
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Quick apply
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs * Support micro ... Prior internship or academic project experience in digital design or verification Marvell's Co-Ops ...
Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs * Support micro ... Prior internship or academic project experience in digital design or verification Marvell's Co-Ops ...
Santa Clara, CA · On-site
$159K/yr
Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs * Support micro ... Prior internship or academic project experience in digital design or verification Marvell's Co-Ops ...
Santa Clara, CA · On-site
$159K/yr
Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs * Support micro ... Prior internship or academic project experience in digital design or verification Marvell's Co-Ops ...
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Youll contribute to RTL design, simulations, and performance optimization for real-world AI ...
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Youll contribute to RTL design, simulations, and performance optimization for real-world AI ...
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... You'll contribute to RTL design, simulations, and performance optimization for real-world AI ...
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... You'll contribute to RTL design, simulations, and performance optimization for real-world AI ...
San Jose, CA · On-site
This internship is ideal for a student with strong fundamentals in analog/RF circuit design who ... Responsibilities As an RFIC Design Engineer Intern, you will: * Assist with the design and ...
San Jose, CA · On-site
This internship is ideal for a student with strong fundamentals in analog/RF circuit design who ... Responsibilities As an RFIC Design Engineer Intern, you will: * Assist with the design and ...
This internship is ideal for a student with strong fundamentals in analog/RF circuit design who ... Responsibilities As an RFIC Design Engineer Intern, you will: * Assist with the design and ...
This internship is ideal for a student with strong fundamentals in analog/RF circuit design who ... Responsibilities As an RFIC Design Engineer Intern, you will: * Assist with the design and ...
What You Can Expect * Own and drive PCIE/CXL subsystem micro-architecture definition, RTL ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect * Own and drive PCIE/CXL subsystem micro-architecture definition, RTL ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect * Own and drive PCIE/CXL subsystem micro-architecture definition, RTL ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect * Own and drive PCIE/CXL subsystem micro-architecture definition, RTL ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... every stage - from internship to retirement and through life's most important moments. Our ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... every stage - from internship to retirement and through life's most important moments. Our ...
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
$10.65 - $13.57
9% of jobs
$13.57 - $16.50
8% of jobs
$17.26 is the 25th percentile. Wages below this are outliers.
$16.50 - $19.43
28% of jobs
The median wage is $20.21 / hr.
$19.43 - $22.36
16% of jobs
$24.36 is the 75th percentile. Wages above this are outliers.
$22.36 - $25.29
20% of jobs
$25.29 - $28.22
9% of jobs
$28.22 - $31.15
4% of jobs
$31.15 - $34.07
1% of jobs
$34.07 - $37
1% of jobs
$37 - $39.93
1% of jobs
$39.93 - $42.86
2% of jobs
$10
$22
$42
| Aspect | Internship Rtl Design Intern | Digital IC Design Intern |
|---|---|---|
| Required Skills | Verilog/VHDL, basic digital design | Verilog/VHDL, digital circuit design, simulation |
| Work Environment | Design teams, hardware development labs | Design teams, hardware development labs |
| Industry Usage | Common in semiconductor and electronics companies | Common in semiconductor and electronics companies |
| Focus Area | RTL coding, simulation, verification | RTL coding, synthesis, timing analysis |
Both roles involve digital design and RTL coding, but the Internship Rtl Design Intern typically focuses on writing and verifying RTL code, while the Digital IC Design Intern may also involve synthesis and timing analysis. They share similar environments and industry usage, making them closely related internship options for aspiring hardware engineers.

Other
Posted 21 days ago
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Familiarity with numerical representations and functions (RTL)
Familiarity with clocking and reset schemes (RTL/PD)
UVM or formal verification experience (DV)
Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.