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Internship Formal Verification Engineer Jobs in Arizona

RTL Design Engineer

Chandler, AZ · On-site

$127K - $203K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Conduct formal verification of design with Synopsys Formality / Cadence Conformal. * Generate ...

Senior Test Engineer

Tucson, AZ · On-site

$125K - $175K/yr

Support test readiness reviews, safety reviews, range testing, and formal verification activities. * Analyse test data and provide clear technical recommendations to engineering and leadership.

Senior Test Engineer

Tucson, AZ · On-site

$125 - $175/hr

Support test readiness reviews, safety reviews, range testing, and formal verification activities. * Analyse test data and provide clear technical recommendations to engineering and leadership.

Head of Engineering About Us Powerlattice is a well-funded semiconductor start-up company backed by ... Formal verification experience is a plus Compensation & Benefits Anticipated annual base salary for ...

New

Senior Test Engineer

Tucson, AZ · On-site

$125K - $175K/yr

Support test readiness reviews, safety reviews, range testing, and formal verification activities. * Analyse test data and provide clear technical recommendations to engineering and leadership.

Experience with formal verification, SI/PI analysis, or mixed-signal hardware. Why Join Moog? Work on cutting-edge spacecraft and defense programs, influence technical direction as a Staff Engineer ...

Experience with formal verification, SI/PI analysis, or mixed-signal hardware. Why Join Moog? Work on cutting-edge spacecraft and defense programs, influence technical direction as a Staff Engineer ...

Experience with formal verification, SI/PI analysis, or mixed-signal hardware.**Why Join Moog?**Work on cutting-edge spacecraft and defense programs, influence technical direction as a Staff Engineer ...

Sr. Avionics RF Engineer

Phoenix, AZ · On-site

$156K - $219K/yr

In addition, you will follow avionics designs through formal verification, environmental ... YourresponsibilitiesasanRFSenior Electrical Engineer will gobeyond thetechnicalaspectsof the ...

New

Demonstrated experience with system engineering principles such as defining requirements and formal verification and validation methods * Test scripting understanding/execution for in-vehicle test ...

Showing results 41-60

Internship Formal Verification Engineer information

What is the difference between Internship Formal Verification Engineer vs Formal Verification Engineer?

AspectInternship Formal Verification EngineerFormal Verification Engineer
QualificationsEnrolled in or recent graduate in Computer Engineering, Electrical Engineering, or related fieldsBachelor's or Master's in Electrical Engineering, Computer Science, or related fields; certifications are a plus
Work EnvironmentInternship programs, entry-level tasks, supervised projectsFull-time professional role, independent project work, team collaboration
Industry UsageCommon in semiconductor, electronics, and hardware companies for trainingEstablished role in hardware design, verification teams, and chip development

The main difference is that an Internship Formal Verification Engineer is a training position for students or recent graduates gaining initial experience, while a Formal Verification Engineer is a full-time professional responsible for verifying hardware designs independently. Interns focus on learning and assisting, whereas full engineers lead verification processes.

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Cities in Arizona with the most Internship Formal Verification Engineer job openings:

RTL Design Engineer

Broadcom

Chandler, AZ • On-site

$127K - $203K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 4 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers


Job description

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Job Description:

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/SystemVerilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Job Requirements

  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications

  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$127,100- $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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