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Internship Book Layout Design Jobs (NOW HIRING)

Intel

Memory Circuit Design Engineer

Austin, TX · On-site

Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory ... PhD with 1-2 years of professional experience gained through either internships or full-time ...

Micron Technology

Intern - DRAM Design Rules

Boise, ID · On-site

Coursework, research, or project experience in VLSI Design, Physical Design, Layout Design, Design ... Exposure through coursework, research, or internship experience to semiconductor test chip design ...

Micron

Intern - DRAM Design Rules

Boise, ID · On-site

Coursework, research, or project experience in VLSI Design, Physical Design, Layout Design, Design ... Exposure through coursework, research, or internship experience to semiconductor test chip design ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

RC extraction, Static Timing Analysis (STA), IR/EM analysis (IREM), Design Rule Check (DRC), Layout ... Prior internship or professional experience in physical design, circuit design, or related ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

RC extraction, Static Timing Analysis (STA), IR/EM analysis (IREM), Design Rule Check (DRC), Layout ... Prior internship or professional experience in physical design, circuit design, or related ...

Three Point Solutions

Graphic Designer

Lafayette, CO · On-site

$40 - $45/hr

Perform detailed document formatting and layout design * Conduct self-reviews and peer reviews for quality assurance * Maintain large, complex documents using InDesign Book features * Collaborate ...

Daktronics

Mechanical Design Co-op Intern

Brookings, SD · On-site

$21 - $23/hr

Our internships and student positions offer hands-on experience, mentorship, and the opportunity to ... Utilize good design methodologies to layout design sets, create pros/cons, and appropriate ...

Daktronics

Mechanical Design Co-op Intern

Brookings, SD · On-site

$21 - $23/hr

Our internships and student positions offer hands-on experience, mentorship, and the opportunity to ... Utilize good design methodologies to layout design sets, create pros/cons, and appropriate ...

Garmin Ltd.

Industrial Engineer 2 - Distribution

Olathe, KS · On-site

$67K - $91K/yr

Provide analysis and input on physical layout design of workspaces for maximum flexibility and ... Outstanding academics (cumulative GPA greater than or equal to 3.5) * Previous work or internship ...

MKC

2027 Summer Intern - Communications

Wichita, KS · On-site

$13.50 - $18/hr

You will assist with the layout, design and writing of our newsletter and other publications, as well as content generation and social media postings. To be successful in this internship, applicants ...

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Internship Book Layout Design information

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$36

How much do internship book layout design jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for internship book layout design in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is an internship in book layout design?

An Internship in Book Layout Design is a temporary position, typically for students or recent graduates, where individuals gain hands-on experience in arranging text, images, and other elements within a book. Interns learn about design principles, typesetting, and publishing software such as Adobe InDesign. This role provides practical exposure to the publishing industry and helps develop skills needed for a career in graphic or book design. Interns often work under the guidance of experienced designers and may contribute to both print and digital book projects.

What can I expect from the collaboration process with editors and authors during a book layout design internship?

As a Book Layout Design intern, you'll regularly interact with editors and authors to ensure that the visual presentation aligns with the book's content and vision. You'll often participate in feedback sessions, where you'll need to interpret and implement revisions based on editorial or author input while maintaining design standards. This collaborative process helps you develop strong communication skills and teaches you how to balance creative ideas with practical publishing requirements. It's a great way to gain experience working in cross-functional teams within the publishing industry.

What are the key skills and qualifications needed to thrive as an internship book layout designer, and why are they important?

To thrive as an Internship Book Layout Designer, you need a solid understanding of design principles, typography, and familiarity with publishing standards, typically supported by coursework or a portfolio in graphic design. Proficiency in industry-standard tools such as Adobe InDesign, Photoshop, and Illustrator is commonly required. Attention to detail, creativity, and effective communication are important soft skills that help in collaborating with authors and editors. These abilities ensure that books are visually appealing, readable, and professionally presented, which is critical for successful publication.

What is the difference between Internship Book Layout Design vs Book Layout Designer?

AspectInternship Book Layout DesignBook Layout Designer
CredentialsTypically students or entry-level with basic design skillsProfessional certification or experience in book design
Work EnvironmentInternship setting, often in publishing or design firmsFull-time or freelance in publishing, media, or printing industries
Employer UsageUsed for training and skill developmentUsed for professional book production and publishing projects

Internship Book Layout Design focuses on training and developing skills in book layout within an internship setting, often for students or beginners. Book Layout Designer is a professional role involving creating and refining book layouts for published works. While both roles involve layout skills, internships are entry-level and educational, whereas book layout designers are experienced professionals producing final, publish-ready designs.

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Internship Book Layout Design jobs near you
Infographic showing various Internship Book Layout Design job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

Memory Circuit Design Engineer

Austin, TX • On-site

Intel
Manufacturing • 10K+ employees
Learn more about Intelexternal

Full-time

Medical, Retirement, PTO

Re-posted 8 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

Job description

Job Details:Job Description: 

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
  • Memory bit-cell and complex periphery IC layout and automation.
  • Memory array/IP design, memory circuit innovation, test-chip design.
  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Qualifications:

You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
  • Design trade-offs between power, performance, and area (PPA).
  • Custom digital circuit design, simulation, layout design, and verification.
  • Knowledge of EDA tools used for custom digital and memory circuit design.

Preferred Qualifications:

  • PhD with 1-2 years of professional experience gained through either internships or full-time employment.
  • Design technology co-optimization (DTCO).
  • Post-Si validation experience.
  • Knowledge of the CMOS ASIC design flow.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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