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Senior Book Layout Design Jobs (NOW HIRING)

Nvidia

Senior SRAM Layout Design Engineer

Durham, NC · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

Nvidia

Senior SRAM Layout Design Engineer

Austin, TX · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

Teledyne

Sr. ASIC Layout Design Engineer

Goleta, CA · On-site

$113K - $151K/yr

We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...

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How much do senior book layout design jobs pay per year?

As of Jun 20, 2026, the average yearly pay for senior book layout design in the United States is $105,882.00, according to ZipRecruiter salary data. Most workers in this role earn between $102,000.00 and $109,000.00 per year, depending on experience, location, and employer.
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Senior Book Layout Design jobs near you
Senior Layout Design Engineer

Senior Layout Design Engineer

Xoriant Corporation

San Jose, CA • Hybrid

Other

Posted 21 days ago

Job description

Job Description:

Job Title: "Senior Layout Design Engineer"

Location: San Jose, CA (Onsite, 5 days a week)

Duration: Long Term

Description

Client is looking for a talent that has strong background and hands-on experience on RF/Analog circuit layout design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits for wireless communication systems along with circuit designers.

Requirements

  • Associate and Bachelor's Degree with 10+ years of relevant industry experience in Electrical Engineering, Technical, or related field preferred.
  • Extensive experience in analog/mixed-signal layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET technologies.
  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports.
  • Extensive experience in analog/RF related circuit layout, including LNA/PA/PLLs and etc.
  • High level of proficiency in CADENCE or MENTOR GRAPHICS layout tools.
  • Good communication skills with design leads as well as engineers for schedule planning.
  • Being able to lead a small group of layout engineers to deliver a successful tapeout.
  • Programming knowledge in SKILL, Perl, and/or Python is a bonus.
  • You re inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You re collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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