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Senior Book Layout Design Jobs (NOW HIRING)

Retym

Senior Layout Designer

Austin, TX · On-site

$101K - $108K/yr

Expertise in technical leading high speed low noise layout design * Expertise in Cadence Layout tools * TSMC FIN FET and/or Gate All Around technologies design * Good understanding of schematic flow

Nvidia

Senior Mask Design Engineer

Santa Clara, CA · Hybrid

$122K - $164K/yr

Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...

Hoskinson Biotechnology

TTRPG Creative Writer

Gillette, WY · On-site

$52K - $70K/yr

Layout Aptitude: A solid understanding of how writing interacts with book layout design. Direct experience with layout software (e.g., InDesign) or formatting is a massive plus. * Attention to Detail:

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How much do senior book layout design jobs pay per year?

As of Jul 10, 2026, the average yearly pay for senior book layout design in the United States is $105,882.00, according to ZipRecruiter salary data. Most workers in this role earn between $102,000.00 and $109,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Senior Book Layout Design jobs? Cities with the most Senior Book Layout Design job openings:
What are the most commonly searched types of Book Layout Design jobs? The most popular types of Book Layout Design jobs are:
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Senior Book Layout Design jobs near you
Infographic showing various Senior Book Layout Design job openings in the United States as of July 2026, with employment types broken down into 84% Full Time, 11% Part Time, 1% Temporary, and 4% Contract. Highlights an 90% Physical, 2% Hybrid, and 8% Remote job distribution, with an average salary of $105,882 per year, or $50.9 per hour.
Sr. Analog Physical Design Engineer

Sr. Analog Physical Design Engineer

OMNIVISION

Santa Clara, CA • On-site

$156K - $160K/yr

Full-time

Re-posted 17 days ago

Job description

Job Title: Sr. Analog Physical Design Engineer
 
Job Duties:
 
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC’s performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. 
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out. 
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices. 
 
Requirements:
 
Require Master’s degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
 
Require 2 years of experience in CMOS image sensor IC layout design.
 
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications. 
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P. 
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such as common-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
 
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
 

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