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Ic Package Layout Designer Jobs (NOW HIRING)

Lightmatter

Package Layout Engineer

Mountain View, CA · Hybrid

... IC codesign. * Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout ... Altium, etc.). * Experience with layout tool scripting languages (e.g., SKILL or Python) to enable ...

Cisco

IC Package Layout Team Leader

San Jose, CA · On-site

$210K - $305K/yr

Your Impact As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance ...

Lightmatter

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

... IC codesign. * Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout ... Altium, etc.). * Experience with layout tool scripting languages (e.g., SKILL or Python) to enable ...

Socket.dev

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

... IC codesign. * Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout ... Altium, etc.). * Experience with layout tool scripting languages (e.g., SKILL or Python) to enable ...

Cisco

IC Package Layout Team Leader

San Jose, CA · On-site

$210K - $305K/yr

Your Impact As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power ...

DensityAI

Package Layout Engineer

Mountain View, CA · On-site

You'll sit between the die and the board, co-designing with physical design on one side and PCB ... Own package substrate and interposer layout end to end; stackup definition, bump and ball map ...

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How much do ic package layout designer jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for ic package layout designer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

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Infographic showing various Ic Package Layout Designer job openings in the United States as of July 2026, with employment types broken down into 80% Full Time, 10% Part Time, and 10% Contract. Highlights an 80% Physical, 2% Hybrid, and 18% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

Package Layout Engineer

Mountain View, CA • Hybrid

Lightmatter
See more jobs at Lightmatterexternal

Full-time

Posted 22 days ago

Job description

About This Role

Lightmatter is looking for a Package Layout Design Engineer to drive the next generation products from concept to development. You will be part of the Signal Integrity, Power Integrity and Packaging team, tasked with delivering substrate layouts that support the package architecture from concept, through design optimization and completion, meeting stringent signal integrity, power integrity, and design for manufacturing requirements. This position offers a unique opportunity to work on new package architectures by solving complex interactions across digital, analog and photonics domains. 

Responsibilities
  • Deliver IC package substrate layouts for standard and advanced packaging technologies.
  • Contribute to the product concept phase by delivering preliminary substrate designs and floorplanning to support overall stack-up (Silicon/package/MB) optimization.
  • Collaborate with package substrate suppliers and Outsourced Semiconductor Assembly and Test (OSAT) companies to apply layout design rules, stack up, and implementation guidelines.
  • Generate fab files and coordinate with substrate suppliers and OSATs to support Design for Manufacturing (DFM) and Design for Assembly (DFA) closure.
  • Design package layouts while adhering to signal integrity, power integrity, thermal, and mechanical requirements.
  • Design packages incorporating analog and digital elements/interfaces.
  • Support signal/power integrity engineers by providing iterative test routes to refine design rules and routing topologies.
  • Coordinate across functional teams to execute error-free Package Design Tape Outs on schedule.
  • Support and adapt design automation and verification activities to improve team efficiency.
Qualifications
  • B.S. or M.S. degree in Electrical Engineering or similar discipline with at least 5 years of relevant experience
  • Minimum 3-5 years of experience in IC package layout design.
  • Proficient with Allegro X APD.
  • Understanding of IC package substrates and organic materials, and their impact on package design.
Preferred Qualifications
  • Educational background in IC packaging and substrate layout design.
  • Familiarity with system-level validation tools such as Cadence Integrity 3DIC for package/IC codesign.
  • Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout, Altium, etc.).
  • Experience with layout tool scripting languages (e.g., SKILL or Python) to enable design automation.
  • Exposure to or interest in early-stage architectural pathfinding and physical feasibility studies for multi-chiplet and advanced packaging architectures (2.5D/3D IC, Silicon Interposers, EMIB, Fan-Out Chip-on-Wafer, etc.).
  • Experience evaluating floorplans, escape routing, bump patterns (micro-bumps / hybrid bonding), and die-to-die (D2D) interface topologies.
  • Excellent communication skills and the ability to collaborate effectively in cross-functional teams.

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