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Ic Layout Design Jobs (NOW HIRING)

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

Qorvo, Inc.

Staff Layout Design Engineer

Denver, CO · On-site

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

Qorvo, Inc.

Staff Layout Design Engineer

Austin, TX

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

Qorvo, Inc.

Staff Layout Design Engineer

Tallahassee, FL · On-site

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

Micron

Staff Layout Designer - Pathfinding

Boise, ID · On-site

IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and Leveraging Artificial Intelligence (AI) to layout workflow As a world leader in the semiconductor industry, Micron is ...

Qorvo, Inc.

IC Layout Engineering Intern

Richardson, TX · On-site

$31 - $42/hr

Learn and apply foundry PDK design rules and layout methodologies. * Support block level floor ... Coursework or projects involving IC physical design or VLSI layout. * Familiarity with Cadence ...

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $141/hr

IC layout design experience with NAND, DRAM and/or SRAM * Good understanding of Claude or Agentic AI or willingness to learn and help develop efficient workflow. * Programming skills and AI ...

Micron

Staff Layout Designer

San Jose, CA · On-site

$72 - $141/hr

IC layout design experience with NAND, DRAM and/or SRAM * Good understanding of Claude or Agentic AI or willingness to learn and help develop efficient workflow. * Programming skills and AI ...

Qorvo, Inc.

IC Layout Engineering Intern

Richardson, TX · On-site

$31 - $42/hr

Learn and apply foundry PDK design rules and layout methodologies. * Support block level floor ... Coursework or projects involving IC physical design or VLSI layout. * Familiarity with Cadence ...

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IC Layout Design information

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How much do ic layout design jobs pay per hour?

As of Sep 15, 2026, the average hourly pay for ic layout design in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What is IC layout design?

IC Layout Design refers to the process of creating the physical layout of integrated circuits (ICs) on a semiconductor chip. It involves translating circuit schematics into geometric patterns that define the placement of transistors, interconnections, and other components on silicon. IC layout designers use specialized software tools to ensure that the design meets electrical, timing, and manufacturing requirements. This step is critical in the semiconductor manufacturing process, as it directly impacts the performance, size, and yield of the final IC.

What are the key skills and qualifications needed to thrive as an IC layout designer, and why are they important?

To thrive as an IC Layout Designer, you need a solid background in electronics or electrical engineering, with expertise in semiconductor device physics and circuit design principles. Familiarity with EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of industry standards like DRC/LVS are typically required. Attention to detail, problem-solving skills, and effective communication are crucial soft skills for collaborating with design and verification teams. These abilities are essential to ensure high-quality, manufacturable layouts that meet performance and reliability requirements in the competitive semiconductor industry.

What are some common challenges IC layout design engineers face when collaborating with circuit designers?

IC Layout Design engineers often work closely with circuit designers to translate schematic designs into physical layouts, which can present challenges such as resolving design-rule violations, managing tight space constraints, and ensuring signal integrity. Effective communication is essential to address trade-offs between performance, area, and manufacturability. Timely feedback loops and a collaborative approach help ensure that both the layout and schematic meet project specifications and timelines.

What is the difference between Ic Layout Design vs IC Design Engineer?

AspectIC Layout DesignIC Design Engineer
Primary FocusCreating physical layouts of integrated circuitsDesigning circuit schematics and functional architecture
Skills RequiredCAD tools, layout optimization, fabrication process knowledgeCircuit theory, HDL coding, simulation
Work EnvironmentEDA tools, cleanroom facilities, collaboration with fabrication teamsDesign teams, simulation labs, software environments
CertificationsTypically none required, but certifications in CAD tools are beneficialEE degree, possibly certifications in digital design or verification

IC Layout Design focuses on physically implementing circuit designs on silicon, while IC Design Engineer involves creating the circuit architecture and logic. Both roles are essential in chip development, often working closely but with distinct skill sets and responsibilities.

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IC Layout Design jobs near you
Infographic showing various Ic Layout Design job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 88% Full Time, 8% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.

Substrate IC Package Layout Design Engineer

San Jose, CA • On-site

Etched
See more jobs at Etchedexternal

$2.0K/mo

Full-time

Medical, Dental, Vision

Posted 18 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job SummaryAs a Substrate IC Package Layout Design Engineer you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co-design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what's possible.
Key Responsibilities
  • IC Substrate Layout Design
  • Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
  • Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
  • Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
  • High-Speed Signal Routing & Integrity
  • Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
  • Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
  • Advanced Packaging & CoWoS Integration
  • Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
  • Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
  • Design Validation & Verification
  • Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
  • Develop and maintain design documentation and guidelines for future substrate designs.
  • Support design reviews and provide technical guidance to junior team members.

You may be a good fit if you have
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
  • Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
  • Proven experience with high-power (700W+) package designs and robust power delivery networks.
  • Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
  • Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos.
  • Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).
  • Deep understanding of SI/PI principles and how they apply to package-level design.
  • Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.

Benefits
  • Medical, dental, and vision packages with generous premium coverage
    • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch and dinner in our office
  • Unlimited compute budget subject to ROI justification

How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

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