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$94,740.00/yr - $227,376.00/yr

Berkeley Lab’s Applied math and Computational Sciences Division has an opening for a Beyond Moore Computational Research Scientist to evaluate and develop devices to hardware/circuit co‑design flow for architectural specializations for high performance computing neuromorphic and edge computing applications.

In the absence of Moore’s Law Scaling, the DOE must investigate alternative paths to continuing computing performance improvements for scientific applications through architectural specialization. Since the beginning of the microchip, we have become accustomed to Moore’s Law relentlessly delivering a doubling of performance, energy efficiency, and density for high‑performance computing (HPC) (and all electronic devices) every 18–24 months. This expectation has led to a relatively stable ecosystem built around general‑purpose processor technologies such as the x86, ARM, and Power instruction set architectures. However, with the tapering of lithography improvements, shrinking transistors can no longer be relied on exclusively to deliver continued performance improvements in digital electronics.

Absent a new transistor technology to replace CMOS, the primary opportunity for continued performance improvement for digital electronics and HPC is to make more efficient use of transistors through architecture specialization, application‑specific acceleration, and compilers/programming‑models that better control data movement than those available today. The successful applicant will contribute to the development and evaluation of novel heterogeneous devices based circuit design for extreme heterogeneous SoC (System on Chip) designs, and evaluate their merit for emerging computational workloads for the purpose of maximizing performance and energy efficiency. This work will have a broad impact on high performance and other larger‑scale computing for critical applications for society and science. The successful applicant will need to have expertise with computer architecture and processor design from the ground up, and have skills in Spice analog/digital circuit design, Verilog and use of CAD/EDA tools; it is also beneficial if the candidate has experience with full tape‑out experience of ASICs. Using those skills, the successful applicant will design post‑Moore device‑based compute, memory, or data transfer blocks for key application kernels to demonstrate the merit of this approach. The applicant will also make key intellectual contributions and consequently publish papers to the emerging field of extreme heterogeneous computing and domain‑specific specializations. Knowledge of processor design techniques like Logic‑In‑Memory/In‑Memory Computing, Spiking Neural Network (SNN) architectures and multivalued logic design techniques is a bonus.

• Design circuits, hardware accelerators and processor architectures using post‑Moore devices to accelerate key HPC applications and application kernels.
• Develop compact models and methodologies to use these circuits for performance and energy characterizations which can be used in architectural simulation framework for tightly integrating these accelerators into heterogeneous systems and SoCs that may contain multiple different kinds of accelerator devices.
• Identify opportunities and challenges for devices to architectural design space exploration for several post‑Moore devices to address those bottlenecks and develop circuit design models to determine the performance potential for those solutions.
• Develop architectural and circuit models for emulation in FPGA hardware.
• Develop metrics and benchmark tests to compare conventional CMOS‑based processors/accelerators and enhanced post‑Moore device‑based computational accelerators for key HPC applications and algorithms.
• Publish work in academic journals and present it at conferences and workshops.
• Lead and assist in the preparation of proposals for funding.
• Mentor graduate students and postdocs.

• PhD or equivalent in a Computing Science or Computer Engineering‑related scientific discipline.
• Mandatory 3 Years of Postdoctoral research experience or equivalent research experience.
• Past experience in either machine‑learning accelerators or SRAM array design or basic blocks of processor at transistor level and/or superconducting circuit design.
• Courses or experience in CAD for VLSI algorithms and C++ programming.
• Proficient in Spice circuit simulations, Verilog and hardware design in CMOS, FeFET, NCFET etc.
• Familiarity with hardware EDA/CAD tools and evaluation/modelling tools in order to extend existing infrastructure to rapidly evaluate CMOS designs.
• Demonstrated creativity, initiative and ability to design, develop and implement complex solutions in consultation with designated technical expert(s) and/or supervisor.
• Experience and track‑record writing technical papers and reports.
• Experience with the use of script languages and system utilities such as configure, Perl, UNIX shell scripts, and “make.”
• Proven record of working effectively in a team, seeing projects through to completion, meeting deadlines, interacting with users, and thorough documentation of contributions.
• Willingness to learn and develop skills in new topics.

• Previous experience and publications in processing‑in‑memory and logic‑in‑memory architectures is highly desirable.
• Experience with developing computational dynamical systems, including networks of coupled oscillators.
• Experience with computational or systems neuroscience.
• Experience with superconducting circuit simulation and design.
• Experience with neuromorphic computing.
• Experience with coding in C++/Python for CAD tool development for ASIC design.
• Experience with higher‑level hardware design languages (HDLs) such as CHISEL, PyMTL, or others.
• Experience with FPGA design flows.
• Demonstrated ability to lead technical efforts with teams of people will also be beneficial.

• Exceptional health and retirement benefits, including pension or 401K‑style plans.
• A culture where you’ll belong – we are invested in our teams.
• In addition to accruing vacation and sick time, we also have a Winter Holiday Shutdown every year.
• Parental bonding leave (for both mothers and fathers).
• Application date: Priority consideration will be given to candidates who apply by January 20 2026. Applications will be accepted until the job posting is removed.
• Appointment type: This is a full‑time, 2 year, term appointment with the possibility of extension or conversion to a career appointment based upon satisfactory job performance, continuing availability of funds and ongoing operational needs.
• Salary range: The expected salary for this position is $94,740 – $227,376, which fits within the full salary of $126,324 – $176,832 depending upon the candidate’s skills, knowledge, and abilities.
• Background check: This position is subject to a background check. Any convictions will be evaluated to determine if they directly relate to the responsibilities and requirements of the position. Having a conviction history will not automatically disqualify an applicant from being considered for employment.
• Work modality: Work may be performed on‑site, hybrid, full‑time telework. The primary location for this role is Lawrence Berkeley National Lab, 1 Cyclotron Road, Berkeley, CA. Work must be performed within the United States. A REAL ID or other acceptable form of identification is required to access Berkeley Lab sites (for more information click here).
• Seeking additional information about working at Berkeley Lab? Please visit careers.lbl.gov.

The foundation of Berkeley Lab is our Stewardship Values: Team Science, Service, Trust, Innovation, and Respect; and we strive to build community with these shared values and commitments. Berkeley Lab is an Equal Opportunity Employer. We heartily welcome applications from all who could contribute to the Lab's mission of leading scientific discovery, excellence, and professionalism. In support of our rich global community, all qualified applicants will be considered for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, protected veteran status, or other protected categories under State and Federal law.

Berkeley Lab is a University of California employer. It is the policy of the University of California to undertake affirmative action and anti‑discrimination efforts, consistent with its obligations as a Federal and State contractor.

Misconduct Disclosure Requirement: As a condition of employment, the finalist will be required to disclose if they are subject to any final administrative or judicial decisions within the last seven years determining that they committed any misconduct, are currently being investigated for misconduct, left a position during an investigation for alleged misconduct, or have filed an appeal with a previous employer.