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Google Asic Design Jobs (NOW HIRING)

Google

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

... ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. * Design ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...

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Google Asic Design information

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$150.2K

$202K

How much do google asic design jobs pay per year?

As of Sep 12, 2026, the average yearly pay for google asic design in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a Google ASIC Design?

A Google ASIC Design job involves developing custom application-specific integrated circuits (ASICs) to optimize performance, power efficiency, and functionality for Google's hardware infrastructure. Engineers in this role work on architecture, design, verification, and testing of ASICs used in data centers, AI accelerators, and other specialized hardware. They collaborate with cross-functional teams to refine system requirements and ensure successful silicon implementation. Strong expertise in digital design, hardware description languages (HDLs) like Verilog or VHDL, and synthesis tools is essential.

What does a Google ASIC Design engineer do?

As a Google ASIC Design engineer, your daily responsibilities typically involve defining microarchitectures, designing and verifying digital circuits, running design simulations, and collaborating closely with verification, software, and hardware teams. You’ll use advanced EDA tools to implement and optimize circuits, ensuring they meet strict specifications for power, performance, and area. Regular design reviews, cross-functional brainstorming sessions, and debugging activities are part of the routine. This collaborative environment fosters continual learning and innovation, providing opportunities for both technical growth and career advancement.

What are the key skills and qualifications needed to thrive in the Google ASIC Design position?

To thrive as a Google ASIC Design engineer, you need a solid background in electrical engineering, digital logic design, and experience with ASIC design methodologies. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, along with scripting languages like Python or TCL, is essential, and a relevant certification or advanced degree can be advantageous. Strong analytical thinking, teamwork, and clear communication skills are highly valued in this role. These skills ensure high-quality, efficient chip designs that meet rigorous performance, power, and area requirements within a collaborative and fast-paced environment.

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Google Asic Design jobs near you
Infographic showing various Google Asic Design job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 62% In-person, 13% Hybrid, and 25% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Static Timing Analysis Engineer, Full Chip STA

Mountain View, CA • On-site

Google Inc.
Software Development • 10K+ employees
Learn more about Google Inc.external

Other

Re-posted 17 days ago

Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

Job description

Static Timing Analysis Engineer, Full Chip STA
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corporate_fare Google place Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • 8 years of technical experience in silicon timing closure and chip integration.
  • Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
  • Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
Preferred qualifications:
  • Master's degree in Electrical Engineering, Computer Science, or a related field.
  • Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
  • Experience with ASIC design flows and methodology of static timing analysis.
  • Knowledge of semiconductor device physics and transistor characteristics.
  • Ability to deliver high complexity silicon in technology process nodes.
  • Effective skills with scripting languages such as Tcl or Perl.
About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

  • Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
  • Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
  • Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoC’s.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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