ZipRecruiter

Log In

1

Google Asic Design Jobs (NOW HIRING)

Google

Signal and Power Integrity Engineer

Sunnyvale, CA · On-site

$196K/yr

Experience in co-design with chip top design, physical design, STA, package, system and validation ... The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the ...

Google

Memory System Architect, Silicon

Mountain View, CA · On-site

$286.70K/yr

... design of ASIC blocks. * Experience in designing/implementing Register-Transfer Level (RTL) for one ... Google's mission is to organize the world's information and make it universally accessible and ...

Google

Sensors Hardware Engineer, Health

Mountain View, CA · On-site

$145.70K - $192.30K/yr

... and ASIC for Google's wearables year after year. You will be responsible for prototyping new ... Learn more about benefits at Google . Responsibilities * Design, analyze, prototype and validate ...

Google

Hardware Power Test Engineer, Platforms

Sunnyvale, CA · On-site

$144.90K - $191.30K/yr

... design to ASIC power integrity validation. * Support design engineers with debug, component ... Google is proud to be an equal opportunity and affirmative action employer. We are committed to ...

Etched

IT Engineer

San Jose, CA · On-site

$150K - $250K/yr

Provide hands-on IT delivery and support for the entire firm, including ASIC design teams, software ... Automate user provisioning and deprovisioning workflows using Rippling, Okta, Google Workspace, and ...

Etched

IT Engineer

San Jose, CA · On-site

$150K - $250K/yr

Provide hands-on IT delivery and support for the entire firm, including ASIC design teams, software ... Automate user provisioning and deprovisioning workflows using Rippling, Okta, Google Workspace, and ...

Aalyria

Lead RTL/FPGA Design Engineer

$170K - $195K/yr

With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and ... Familiarity with high-speed ASIC/FPGA synthesis, place and route (P&R), and static timing analysis ...

Aalyria

Communications DSP Engineer

$185K - $215K/yr

With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and ... You'll collaborate closely with cross-functional teams spanning ASIC/FPGA design, RF/optical ...

AFL

... Google, and Nvidia, while expanding influence to custom ASIC designers requiring specialized ... Deep familiarity with the design cycles and qualification processes of major hardware manufacturers.

Etched

Chip Simulation Software Engineer

San Jose, CA · On-site

$200K - $250K/yr

... ASIC that leverages tight hardware-software co-design to deliver world-best performance. The chip ... Experience with custom ML hardware accelerators (e.g., Google TPU) * Experience with firmware ...

Etched

Chip Simulation Software Engineer

San Jose, CA · On-site

$200K - $250K/yr

... ASIC that leverages tight hardware-software co-design to deliver world-best performance. The chip ... Experience with custom ML hardware accelerators (e.g., Google TPU) * Experience with firmware ...

next page

Showing results 1-20

People also search for

All JobsGoogle Asic Design Jobs

Google Asic Design information

See salary details

$94K

$150.2K

$202K

How much do google asic design jobs pay per year?

As of May 30, 2026, the average yearly pay for google asic design in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a Google ASIC Design job?

A Google ASIC Design job involves developing custom application-specific integrated circuits (ASICs) to optimize performance, power efficiency, and functionality for Google's hardware infrastructure. Engineers in this role work on architecture, design, verification, and testing of ASICs used in data centers, AI accelerators, and other specialized hardware. They collaborate with cross-functional teams to refine system requirements and ensure successful silicon implementation. Strong expertise in digital design, hardware description languages (HDLs) like Verilog or VHDL, and synthesis tools is essential.

What are the key skills and qualifications needed to thrive in the Google Asic Design position, and why are they important?

To thrive as a Google ASIC Design engineer, you need a solid background in electrical engineering, digital logic design, and experience with ASIC design methodologies. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, along with scripting languages like Python or TCL, is essential, and a relevant certification or advanced degree can be advantageous. Strong analytical thinking, teamwork, and clear communication skills are highly valued in this role. These skills ensure high-quality, efficient chip designs that meet rigorous performance, power, and area requirements within a collaborative and fast-paced environment.

What does the day-to-day work look like for a Google ASIC Design engineer?

As a Google ASIC Design engineer, your daily responsibilities typically involve defining microarchitectures, designing and verifying digital circuits, running design simulations, and collaborating closely with verification, software, and hardware teams. You’ll use advanced EDA tools to implement and optimize circuits, ensuring they meet strict specifications for power, performance, and area. Regular design reviews, cross-functional brainstorming sessions, and debugging activities are part of the routine. This collaborative environment fosters continual learning and innovation, providing opportunities for both technical growth and career advancement.
More about Google Asic Design jobs
What cities are hiring for Google Asic Design jobs? Cities with the most Google Asic Design job openings:
What states have the most Google Asic Design jobs? States with the most job openings for Google Asic Design jobs include:
What job categories do people searching Google Asic Design jobs look for? The top searched job categories for Google Asic Design jobs are:
Google Asic Design jobs near you
Infographic showing various Google Asic Design job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 49% In-person, 13% Hybrid, and 38% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Senior Signal and Power Integrity Engineer

Google

Sunnyvale, CA • On-site

$196K/yr

Full-time

Posted 25 days ago

Google rating

8.7

Company rating: 8.7 out of 10

Based on 91 frontline employees who took The Breakroom Quiz

36th of 183 rated software companies

Job description

Minimum qualifications:
  • Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
  • 4 years of experience in SI/PI design for chip/package or system PCB.
  • Experience in industry SI/PI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Experience with signal and power integrity with various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe, etc.).
  • Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
  • Experience in co-design with chip top design, physical design, STA, package, system and validation teams.
  • Familiarity with the post SI test environment on memory or high speed serdes.
  • Excellent programming and data analysis skills with MATLAB, Python, C , etc. to establish automation flows and data processing.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Chip Package Signal Integrity/Power Integrity (SI/PI) Engineer, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level. Within a concurrent engineering environment, you will be the main part of a larger team with system architects, ASIC engineers, and other SI/PI engineers. You will work with multi cross-functional teams including chip design team, board design team, system design team as well as vendors. You will drive chip packaging signal and power implementations to meet chip, package and system electrical requirements.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
  • Drive SI/PI analysis and optimization for HPC based on 2.5D/3D technology, influencing product definition, chip floorplan, power tree structures, and netlists.
  • Lead the development of next-generation memory interfaces and evaluate high-speed interface IP, considering Input/Output Physical Layer (IO PHY), physical design, and SI/PI requirements.
  • Manage post-silicon validation and qualification of high-speed interfaces for New Product Introduction (NPI), ensuring performance meets production standards.
  • Partner with chip/system design teams and external vendors to define SI/PI design goals, set chip boundaries, and balance SI/PI and DFM tradeoffs for production closure.
  • Develop innovative methodologies to enhance simulation accuracy and productivity while providing critical feedback on chip floorplans to optimize routability and signal integrity.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

What Google employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply