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Google Asic Design Jobs (NOW HIRING)

ML ASIC Design Engineer

Mountain View, CA · On-site

$175K - $215K/yr

Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Perform power, area and performance exploration and optimization of digital ASIC designs * Design ...

ASIC Design Verification Engineer, TPU

Sunnyvale, CA · On-site

$159K - $194K/yr

As an ASIC Design Verification Engineer, you will use design and verification expertise to verify ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...

Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Perform power, area and performance exploration and optimization of digital ASIC designs * Design ...

Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Perform power, area and performance exploration and optimization of digital ASIC designs * Design ...

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Google Asic Design information

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$94K

$150.2K

$202K

How much do google asic design jobs pay per year?

As of Aug 21, 2026, the average yearly pay for google asic design in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a Google ASIC Design?

A Google ASIC Design job involves developing custom application-specific integrated circuits (ASICs) to optimize performance, power efficiency, and functionality for Google's hardware infrastructure. Engineers in this role work on architecture, design, verification, and testing of ASICs used in data centers, AI accelerators, and other specialized hardware. They collaborate with cross-functional teams to refine system requirements and ensure successful silicon implementation. Strong expertise in digital design, hardware description languages (HDLs) like Verilog or VHDL, and synthesis tools is essential.

What does a Google ASIC Design engineer do?

As a Google ASIC Design engineer, your daily responsibilities typically involve defining microarchitectures, designing and verifying digital circuits, running design simulations, and collaborating closely with verification, software, and hardware teams. You’ll use advanced EDA tools to implement and optimize circuits, ensuring they meet strict specifications for power, performance, and area. Regular design reviews, cross-functional brainstorming sessions, and debugging activities are part of the routine. This collaborative environment fosters continual learning and innovation, providing opportunities for both technical growth and career advancement.

What are the key skills and qualifications needed to thrive in the Google ASIC Design position?

To thrive as a Google ASIC Design engineer, you need a solid background in electrical engineering, digital logic design, and experience with ASIC design methodologies. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, along with scripting languages like Python or TCL, is essential, and a relevant certification or advanced degree can be advantageous. Strong analytical thinking, teamwork, and clear communication skills are highly valued in this role. These skills ensure high-quality, efficient chip designs that meet rigorous performance, power, and area requirements within a collaborative and fast-paced environment.

More about Google Asic Design jobs

What cities are hiring for Google Asic Design jobs?

Cities with the most Google Asic Design job openings:

What states have the most Google Asic Design jobs?

States with the most job openings for Google Asic Design jobs include:

Infographic showing various Google Asic Design job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC Design Verification Manager, Google Cloud

Google Inc.

Sunnyvale, CA • On-site

$192 - $278/hr

Other

Posted 23 days ago


Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

48th of 245 rated software companies


Job description

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Google Sunnyvale, CA, USA

Advanced

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders;deep expertise in domain.

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience with verification, SystemVerilog, and UVM.
  • 3 years of experience in people management.
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.
  • Knowledge of general purpose operating systems such as Linux and Android.
  • Familiarity with ARM Instruction Set Architecture.
About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at the subchip, subsystem, and full-chip levels. This includes developing comprehensive test plans, writing diagnostic codes, and building monitors and checkers to ensure quality assurance. Additionally, you will partner closely with front-end design, architecture, and performance teams. By analyzing coverage across multiple dimensions, you will help ensure architectural compliance, verify functional correctness, and guide your team to meet key performance goals.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at the subchip, subsystem, and full-chip levels. This includes developing comprehensive test plans, writing diagnostic codes, and building monitors and checkers to ensure quality assurance. Additionally, you will partner closely with front-end design, architecture, and performance teams. By analyzing coverage across multiple dimensions, you will help ensure architectural compliance, verify functional correctness, and guide your team to meet key performance goals.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google .

Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.

  • Define and guide advanced verification strategies, including the use of simulation, for bug hunt, formal verification for corner-case bugs and emulation for system validation.

Partner with front-end design, architecture, and performance teams to help ensure architectural compliance and achievement of performance goals.

  • Analyze coverage from various dimensions and develop monitors and checkers for quality assurance.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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