ASIC Technology Librarian
Sunnyvale, CA · On-site
Demonstrated ability to compile libraries and debug issues across design views (.lib, .db, .ndm ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Sunnyvale, CA · On-site
Demonstrated ability to compile libraries and debug issues across design views (.lib, .db, .ndm ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Sunnyvale, CA · On-site
Demonstrated ability to compile libraries and debug issues across design views (.lib, .db, .ndm ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate ... Google . Responsibilities * Contribute to design power modeling and drive convergence to power ...
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate ... Google . Responsibilities * Contribute to design power modeling and drive convergence to power ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Google's mission is to organize the world's information and make it universally accessible and ...
Sunnyvale, CA · On-site
$163K - $237K/yr
Google, Sunnyvale, CA, USA Qualifications * Bachelor's degree in Electrical Engineering, Computer ... Develop SystemVerilog RTL to implement logic for ASIC products according to coding and quality ...
Sunnyvale, CA · On-site
$163K - $237K/yr
Google, Sunnyvale, CA, USA Qualifications * Bachelor's degree in Electrical Engineering, Computer ... Develop SystemVerilog RTL to implement logic for ASIC products according to coding and quality ...
As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at ...
As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at ...
Sunnyvale, CA · On-site
$237K/yr
About the Team Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of ... Contribute to ASIC design and layout, system-level optimization, and product strategy.
Sunnyvale, CA · On-site
$237K/yr
About the Team Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of ... Contribute to ASIC design and layout, system-level optimization, and product strategy.
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Sunnyvale, CA · On-site
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
Sunnyvale, CA · On-site
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
Google Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more ... Experience with ASIC design methodologies for clock domain checks, reset checks and low power ...
Google Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more ... Experience with ASIC design methodologies for clock domain checks, reset checks and low power ...
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
# Senior ASIC Physical Design EngineerGoogle • onsite • 111 W Java Dr, Sunnyvale, CA 94089, USA ... USD 156000.00 - USD 229000.00 / unspecifiedBusinesses of all shapes and sizes rely on Google ...
# Senior ASIC Physical Design EngineerGoogle • onsite • 111 W Java Dr, Sunnyvale, CA 94089, USA ... USD 156000.00 - USD 229000.00 / unspecifiedBusinesses of all shapes and sizes rely on Google ...
Mountain View, CA · On-site
$175K - $215K/yr
Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Partner with design and architecture teams to translate hardware specifications into comprehensive ...
Mountain View, CA · On-site
$175K - $215K/yr
Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Partner with design and architecture teams to translate hardware specifications into comprehensive ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... or ASIC/SoC design. * Experience with SystemVerilog Assertions (SVA) and formal verification ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... or ASIC/SoC design. * Experience with SystemVerilog Assertions (SVA) and formal verification ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Sunnyvale, CA · On-site
$159K - $164K/yr
... ASIC design environment. * Experience in static low-power rule checking tools (e.g., VCLP or CLP ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Sunnyvale, CA · On-site
$159K - $164K/yr
... ASIC design environment. * Experience in static low-power rule checking tools (e.g., VCLP or CLP ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... design, and assisting in the hardware and lab bring up and verification of our ASIC systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with ...
... design, and assisting in the hardware and lab bring up and verification of our ASIC systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with ...
Experience with ASIC design flows and methodology of static timing analysis. * Knowledge of ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience with ASIC design flows and methodology of static timing analysis. * Knowledge of ... Google's mission is to organize the world's information and make it universally accessible and ...
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
A Google ASIC Design job involves developing custom application-specific integrated circuits (ASICs) to optimize performance, power efficiency, and functionality for Google's hardware infrastructure. Engineers in this role work on architecture, design, verification, and testing of ASICs used in data centers, AI accelerators, and other specialized hardware. They collaborate with cross-functional teams to refine system requirements and ensure successful silicon implementation. Strong expertise in digital design, hardware description languages (HDLs) like Verilog or VHDL, and synthesis tools is essential.
As a Google ASIC Design engineer, your daily responsibilities typically involve defining microarchitectures, designing and verifying digital circuits, running design simulations, and collaborating closely with verification, software, and hardware teams. You’ll use advanced EDA tools to implement and optimize circuits, ensuring they meet strict specifications for power, performance, and area. Regular design reviews, cross-functional brainstorming sessions, and debugging activities are part of the routine. This collaborative environment fosters continual learning and innovation, providing opportunities for both technical growth and career advancement.
To thrive as a Google ASIC Design engineer, you need a solid background in electrical engineering, digital logic design, and experience with ASIC design methodologies. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, along with scripting languages like Python or TCL, is essential, and a relevant certification or advanced degree can be advantageous. Strong analytical thinking, teamwork, and clear communication skills are highly valued in this role. These skills ensure high-quality, efficient chip designs that meet rigorous performance, power, and area requirements within a collaborative and fast-paced environment.
Cities with the most Google Asic Design job openings:
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Sunnyvale, CA • On-site
Full-time
Re-posted 13 days ago
Manage the handoff of library collateral to projects and perform checks to ensure data integrity.
Drive library validation across views using tools like Siemens Solido Crosscheck.
Perform Logic Equivalency Checking (LEC) using tools such as Formality or Conformal.
8.8
Based on 103 frontline employees who took The Breakroom Quiz
Sourced by ZipRecruiter
Software development and technology, communication and media
10,000+ Employees
Mountain View, CA, US