SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$171K - $302K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
$120K - $210K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
$120K - $210K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
$171K - $302K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
$171K - $302K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain ...
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain ...
$120K - $210K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
$120K - $210K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
$23.52 is the 25th percentile. Wages below this are outliers.
$14.90 - $25.57
31% of jobs
The median wage is $32.14 / hr.
$25.57 - $36.23
31% of jobs
$36.23 - $46.90
4% of jobs
$56.23 is the 75th percentile. Wages above this are outliers.
$46.90 - $57.56
10% of jobs
$57.56 - $68.23
9% of jobs
$68.23 - $78.89
5% of jobs
$78.89 - $89.55
0% of jobs
$89.55 - $100.22
8% of jobs
$100.22 - $110.88
0% of jobs
$110.88 - $121.55
0% of jobs
$121.55 - $132.21
1% of jobs
$14
$47
$132
| Aspect | Freelance Soc Design Engineer | Freelance ASIC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering, VLSI, or related fields; certifications in digital/analog design | Bachelor's or Master's in Electrical Engineering, VLSI, or related fields; certifications in ASIC design |
| Work Environment | Designing integrated system-on-chip components, often in collaborative teams or remote freelance projects | Designing custom ASIC chips, typically in specialized design firms or freelance roles |
| Industry Usage | Used in consumer electronics, mobile devices, embedded systems | Used in high-performance computing, telecommunications, specialized hardware |
Both roles involve digital design skills and VLSI knowledge, but Freelance Soc Design Engineers focus on integrating multiple components into a single chip, while Freelance ASIC Design Engineers specialize in creating custom chips for specific applications. The choice depends on the project scope and industry focus.

Sourced by ZipRecruiter
Software development
1,001 - 5,000 Employees
Santa Clara, CA, US
1995