... designed and produced. This is a highly interdisciplinary role that requires strong software ... Work with GDSII and IC layout formats to generate, manipulate, and validate layout data * Develop ...
Quick apply
... designed and produced. This is a highly interdisciplinary role that requires strong software ... Work with GDSII and IC layout formats to generate, manipulate, and validate layout data * Develop ...
Quick apply
... designed and produced. This is a highly interdisciplinary role that requires strong software ... Work with GDSII and IC layout formats to generate, manipulate, and validate layout data * Develop ...
Fremont, CA · On-site
$190K - $220K/yr
... designed and produced. This is a highly interdisciplinary role that requires strong software ... Work with GDSII and IC layout formats to generate, manipulate, and validate layout data * Develop ...
Fremont, CA · On-site
$190K - $220K/yr
... designed and produced. This is a highly interdisciplinary role that requires strong software ... Work with GDSII and IC layout formats to generate, manipulate, and validate layout data * Develop ...
$134K - $201K/yr
Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...
$134K - $201K/yr
Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...
Wilmington, MA · On-site
$159K - $239K/yr
Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Principal Designer, Layout, you are a recognized expert within ADI, working on uniquely ...
Wilmington, MA · On-site
$159K - $239K/yr
Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Principal Designer, Layout, you are a recognized expert within ADI, working on uniquely ...
$159K - $239K/yr
Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Principal Designer, Layout, you are a recognized expert within ADI, working on uniquely ...
$159K - $239K/yr
Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Principal Designer, Layout, you are a recognized expert within ADI, working on uniquely ...
Colorado Springs, CO · On-site
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
Colorado Springs, CO · On-site
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
Cedar Rapids, IA · On-site
$114K - $220K/yr
Requisition ID: 77676 Description Skyworks Cedar Rapids design center is seeking a Senior Principal Layout Designer responsible for the layout of Analog integrated circuits, utilizing commercial ...
Cedar Rapids, IA · On-site
$114K - $220K/yr
Requisition ID: 77676 Description Skyworks Cedar Rapids design center is seeking a Senior Principal Layout Designer responsible for the layout of Analog integrated circuits, utilizing commercial ...
Santa Clara, CA · On-site
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
Santa Clara, CA · On-site
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
$117K - $195K/yr
Through close collaboration with IC designers and experts in IC technologies and IC design tools ... Creating transistor level layout views from schematics, spanning from cell-level up through top ...
Dallas, TX · On-site
... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.
Dallas, TX · On-site
... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.
Dallas, TX · On-site
... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.
Dallas, TX · On-site
... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.
Redmond, WA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Redmond, WA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
San Diego, CA · On-site
QCT WAN RFIC design group is seeking an experienced Mask Layout Designer to fulfill both block and project lead level roles working in a very large team environment. Responsibilities will vary ...
San Diego, CA · On-site
QCT WAN RFIC design group is seeking an experienced Mask Layout Designer to fulfill both block and project lead level roles working in a very large team environment. Responsibilities will vary ...
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers. * Perform physical layout for digital and mixed-signal ...
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers. * Perform physical layout for digital and mixed-signal ...
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers. * Perform physical layout for digital and mixed-signal ...
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers. * Perform physical layout for digital and mixed-signal ...
Irvine, CA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Irvine, CA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
$125K - $155K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
$125K - $155K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Redmond, WA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Redmond, WA · On-site
$115K - $145K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Sunnyvale, CA · On-site
$125K - $155K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
Sunnyvale, CA · On-site
$125K - $155K/yr
You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...
$16.79 is the 25th percentile. Wages below this are outliers.
$10.10 - $18.36
31% of jobs
$18.36 - $26.62
16% of jobs
The median wage is $29.10 / hr.
$26.62 - $34.88
11% of jobs
$34.88 - $43.14
15% of jobs
$48.30 is the 75th percentile. Wages above this are outliers.
$43.14 - $51.40
4% of jobs
$51.40 - $59.66
6% of jobs
$59.66 - $67.92
5% of jobs
$67.92 - $76.18
3% of jobs
$76.18 - $84.44
2% of jobs
$84.44 - $92.70
3% of jobs
$92.70 - $100.96
3% of jobs
$10
$41
$100
| Aspect | Freelance Ic Layout Mask Designer | Freelance Semiconductor Process Engineer |
|---|---|---|
| Credentials | CAD software proficiency, electronics background | Engineering degree, process knowledge |
| Work Environment | Design studios, client sites | Research labs, manufacturing facilities |
| Industry Usage | Integrated circuit manufacturing | Semiconductor fabrication processes |
| Common Search/Comparison | Design focus, mask creation | Process optimization, fabrication |
While both roles are integral to semiconductor manufacturing, Freelance Ic Layout Mask Designers focus on creating detailed circuit layouts and masks, whereas Freelance Semiconductor Process Engineers optimize fabrication processes. The roles differ in their core responsibilities but often collaborate within the industry.

Rigetti is seeking an IC Layout Automation Software Engineer to develop and maintain software systems that support the design and fabrication of superconducting quantum circuits.
This role sits at the intersection of software engineering, IC layout, and semiconductor fabrication, enabling the translation of device and process requirements into manufacturable layouts. You will work closely with cross-functional teams across design, fabrication, and research to build and evolve tools that are critical to how quantum devices are designed and produced.
This is a highly interdisciplinary role that requires strong software fundamentals alongside familiarity with IC design workflows and fabrication processes. You will play a key role in improving the reliability, usability, and scalability of layout generation and design tooling used in a cutting-edge R&D environment and over time, in shaping what that tooling becomes.Â
Design, develop, and maintain production-quality software systems for IC layout generation and design workflows
Refactor and improve existing codebases to increase maintainability, usability, and performance
Build scalable and extensible software architectures that support evolving design and fabrication requirements
Ensure code quality through best practices in testing, documentation, and version control
Translate design and fabrication requirements into layout-ready implementations
Work with GDSII and IC layout formats to generate, manipulate, and validate layout data
Develop and maintain tooling that supports layout generation, verification, and iteration
Integrate software workflows with existing EDA tools and design environments
Partner closely with design, fabrication, and research teams to understand requirements and deliver effective solutions
Collaborate with stakeholders to define workflows and improve how design requests are translated into implementation
Support users across multiple technical domains, improving usability and reducing friction in tooling
Contribute to prioritization discussions across competing stakeholder needs
Improve usability and accessibility of internal design tools to reduce errors and increase efficiency
Identify and address gaps in current workflows, proposing more robust and user-friendly solutions
Support the evolution of tooling from ad hoc usage toward more structured and scalable systems
Balance reactive work (stabilization, bug fixing) with proactive development of new capabilities
B.S., M.S., or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, Physics, Applied Physics, Materials Science, or a related technical field.
Strong proficiency in Python, with experience developing and maintaining production-quality software in a real-world engineering or technical environment.
Proven ability to own and improve complex, long-lived codebases, including refactoring, architecture decisions, testing, documentation, and maintainability.
Experience working with IC layout data and formats, including GDSII.
Familiarity with EDA / IC layout tooling such as KLayout, gdspy, Cadence, or similar platforms.
Strong communication skills, with the ability to operate across teams that use different technical language and workflows.
Working knowledge of semiconductor fabrication workflows, with exposure to lithography processes.
Familiarity with lithography required; experience with e-beam lithography a strong plus.
Ability to translate design, fabrication, or process requirements into reliable software implementations.
Demonstrated ability to work cross-functionally with stakeholders across software, hardware, design, fabrication, and research teams.
Ability to manage ambiguity, prioritize competing requests, and bring structure to evolving technical systems.
Comfortable working closely with cleanroom, fab, or lab-based teams in an R&D environment.
As engineering leaders, we value diversity and are committed to building a culture of inclusion to attract and engage innovative thinkers. Our technology, meant to serve all of humanity, cannot succeed if those who built it do not mirror the diversity of the communities we serve. Applications from women, minorities, and other under-represented groups are encouraged.
We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
Sourced by ZipRecruiter
It services
51 - 200 Employees
Berkeley, CA, US
2013