Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
Emulation Verification Engineer
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
Beaverton, OR · On-site
$120 - $150/hr
... verification of large SoCs ... The overall work will involve porting the design onto the Palladium platform, followed by ...
Emulation Verification Engineer
Beaverton, OR · On-site
$120 - $150/hr
... verification of large SoCs ... The overall work will involve porting the design onto the Palladium platform, followed by ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
RTL Design Engineer
Beaverton, OR · On-site
$120 - $180/hr
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation ...
RTL Design Engineer
Beaverton, OR · On-site
$120 - $180/hr
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation ...
RTL Design Engineer
Beaverton, OR · On-site
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
RTL Design Engineer
Beaverton, OR · On-site
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings)
Portland, OR · On-site
$144K/yr
Bachelor's degree in Electronics or Electrical Engineering, Physics, Computer Science, Computer ... Complete object-oriented design verification. * Develop cutting-edge networking hardware and ...
New
Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings)
Portland, OR · On-site
$144K/yr
Bachelor's degree in Electronics or Electrical Engineering, Physics, Computer Science, Computer ... Complete object-oriented design verification. * Develop cutting-edge networking hardware and ...
New
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
As part of our Silicon Technologies group, you'll help design and manufacture our next-generation ... Python programming background Preferred Qualifications * Experience developing, maintaining, and ...
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
As part of our Silicon Technologies group, you'll help design and manufacture our next-generation ... Python programming background Preferred Qualifications * Experience developing, maintaining, and ...
RTL Design Engineer
Hillsboro, OR · On-site
... and refine verification plans and tests to ensure correct implementation of design features ... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic ...
RTL Design Engineer
Hillsboro, OR · On-site
... and refine verification plans and tests to ensure correct implementation of design features ... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic ...
Entry-Level Stormwater Engineer
Portland, OR · On-site
$52 - $76/hr
... Entry-Level Stormwater Engineer. Responsibilities ... Assisting with the design of stormwater management facilities and other water resources (drinking ...
Entry-Level Stormwater Engineer
Portland, OR · On-site
$52 - $76/hr
... Entry-Level Stormwater Engineer. Responsibilities ... Assisting with the design of stormwater management facilities and other water resources (drinking ...
Design Engineer
Woodland, WA · On-site
$75K - $100K/yr
... Engineer. ESSENTIAL FUNCTIONS * May coordinate multiple small projects or large project ... Model, prototype, and build product concepts; verify the design meets specifications and safety ...
Quick apply
Design Engineer
Woodland, WA · On-site
$75K - $100K/yr
... Engineer. ESSENTIAL FUNCTIONS * May coordinate multiple small projects or large project ... Model, prototype, and build product concepts; verify the design meets specifications and safety ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Hardware Design Engineer
Beaverton, OR · On-site
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
Hardware Design Engineer
Beaverton, OR · On-site
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
Freelance Entry Level Design Verification Engineer information
See Portland, OR salary details
$31.8K - $40.3K
2% of jobs
$40.3K - $48.8K
10% of jobs
$54.4K is the 25th percentile. Wages below this are outliers.
$48.8K - $57.3K
20% of jobs
$57.3K - $65.8K
13% of jobs
The median wage is $67.9K / yr.
$65.8K - $74.2K
21% of jobs
$79.8K is the 75th percentile. Wages above this are outliers.
$74.2K - $82.7K
14% of jobs
$82.7K - $91.2K
7% of jobs
$91.2K - $99.7K
5% of jobs
$99.7K - $108.2K
3% of jobs
$108.2K - $116.7K
2% of jobs
$116.7K - $125.1K
2% of jobs
$31.8K
$73.6K
$125.1K
How much do freelance entry level design verification engineer jobs pay per year?
As of Sep 4, 2026, the average yearly pay for freelance entry level design verification engineer in Portland, OR is $73,559.00, according to ZipRecruiter salary data. Most workers in this role earn between $54,600.00 and $83,200.00 per year, depending on experience, location, and employer.
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For Freelance Entry Level Design Verification Engineer jobs in Portland, OR, the most frequently searched job titles are:
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What job categories do people searching Freelance Entry Level Design Verification Engineer jobs in Portland, OR look for?
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Apple rating
8.1
Based on 681 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area with minimum 3 years of proven experience or equivalent strongly preferred
Strong knowledge of OOP, SystemVerilog and UVM
Strong knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
Some working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
Minimum requirement of a bachelors degree
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area with minimum 3 years of proven experience or equivalent strongly preferred
Strong knowledge of OOP, SystemVerilog and UVM
Strong knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
Some working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
Minimum requirement of a bachelors degree
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976