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Freelance Design Verification Engineer Jobs in Virginia

Fractile

Lead Physical Design Engineer

Bristol, VA · On-site

$120 - $180/hr

You will collaborate with cross-functional teams, including logic design, verification, and process ... Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical ...

New

Eli Lilly and Company

Engineer - Design Lead

Richmond, VA · On-site

$101K - $133K/yr

Participate in the selection of the verification professional services. * Accountable for the ... Engineering Tech Center resources, and design specialists) * Demonstrated values that are ...

Eli Lilly and Company

Engineer - Design Lead

Richmond, VA · On-site

$101K - $133K/yr

Participate in the selection of the verification professional services. * Accountable for the ... Engineering Tech Center resources, and design specialists) * Demonstrated values that are ...

BWXT

Mechanical System Design Engineer

Lynchburg, VA

Experience with design verification including interface with component vendors and test engineering organizations. * System modeling experience in Simulink and exposure to Sysml. * Familiarity with ...

IntelliPro Group Inc.

Civil Design Engineer

Surry, VA · On-site

$90 - $98/hr

Consulting Engineer (Civil/Structural) - Nuclear Projects Location: Surry, VA, 23883 Pay: $90-$100 ... Experience with piping supports, rigging analysis, heavy load evaluations, and design verification.

IntelliPro Group Inc.

Civil Design Engineer

Surry, VA · On-site

$90 - $98/hr

Consulting Engineer (Civil/Structural) - Nuclear Projects Location: Surry, VA, 23883 Pay: $90-$100 ... Experience with piping supports, rigging analysis, heavy load evaluations, and design verification.

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All JobsDesign Verification Engineer JobsFreelance Design Verification Engineer JobsFreelance Design Verification Engineer Jobs in Virginia

Freelance Design Verification Engineer information

What is the difference between Freelance Design Verification Engineer vs Freelance Hardware Test Engineer?

AspectFreelance Design Verification Engineer

Freelance Design Verification Engineers focus on verifying that hardware designs meet specifications through simulation and testing, often working on FPGA, ASIC, or semiconductor projects. They typically hold certifications in digital design and verification tools, and work in industries like semiconductor, electronics, and tech startups. Freelance Hardware Test Engineers, on the other hand, primarily perform physical testing of hardware prototypes and products, focusing on functional and reliability testing in manufacturing environments. While both roles require technical expertise, verification engineers emphasize simulation and design validation, whereas test engineers focus on real-world hardware testing.

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Freelance Design Verification Engineer jobs near you

FPGA Verification Engineer with Security Clearance

Legacy Consulting Services , LLC

Arlington, VA • On-site

$141K - $195K/yr

Other

Re-posted 8 days ago

Job description

Location: Arlington, VA (HQ2) or Jessup, MD Clearance: Active TS/SCI with polygraph required Citizenship: US Citizen required Scope of Work
Develop and execute verification strategies for FPGA-based systems supporting AWS infrastructure. The contractor will build UVM-based verification environments, develop testbenches, and drive coverage closure for 100G+ networking solutions on advanced FPGA platforms. Key Responsibilities
• Develop UVM/SystemVerilog verification environments and testbenches for FPGA designs
• Create and execute verification plans with functional coverage models and assertions
• Drive coverage closure to completion (functional, code, and assertion coverage)
• Debug RTL failures in simulation and on hardware targets
• Develop constrained-random and directed test sequences for protocol verification (e.g., AXI, Ethernet)
• Perform regression analysis and coverage gap identification
• Collaborate with design engineers on architecture reviews and interface specifications
• Support hardware bring-up and debug on FPGA targets Required Qualifications
• BS in Electrical Engineering or related field
• 5+ years FPGA/ASIC verification experience
• SystemVerilog required
• 5+ years with UVM-based verification (constrained-random, coverage-driven methodologies)
• Demonstrated experience driving coverage closure to completion
• Strong UVM testbench architecture skills (agents, sequences, scoreboards, coverage models)
• Proficiency in SystemVerilog assertions (SVA) and simulation tools (Synopsys VCS, Mentor Questa, or equivalent)
• Experience verifying high-speed networking or datapath designs
• Knowledge of standard bus protocols (AXI, AXI-Stream, Ethernet)
• Active TS/SCI with polygraph (US Citizen)

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