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Freelance Asic Rtl Design Engineer Jobs in Cleveland, OH

Innovative Technology Company focused on Essential Industry Customers

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Senior ASIC Design Engineer, Analog and Power, remote OK

Mentor, OH · Remote

$125K - $165K/yr

You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design, simulation, verification, and delivery of custom ASICs focused on power/voltage conversion ...

New

Afference

ASIC Engineer

Cleveland, OH · On-site

$116K - $174K/yr

Help shape the design and development of ASIC chips under the guidance of senior engineers and leadership. * Collaborate with product teams to align ASIC design efforts with customer requirements.

Innovative Technology Company focused on Essential Industry Customers

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Senior PCB Design, small-discreet boards, remote or hybrid or on-site

Akron, OH · On-site

$125K - $165K/yr

Senior PCB Design & Layout Engineer - Power Management & Flexible Voltage Systems Bleeding Edge ... Partner with ASIC, firmware, and mechanical engineers to integrate custom blocks and ensure system ...

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company826

Supervisor, Learning Media

Cleveland, OH · On-site

The position applies advanced multimedia design expertise, project management, coaching, and broad ... Sources and manages freelancers and contractors. * Collaborates with Subject Matter Experts (SMEs ...

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Freelance Asic Rtl Design Engineer information

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$14

$46

$128

How much do freelance asic rtl design engineer jobs pay per hour?

As of Sep 1, 2026, the average hourly pay for freelance asic rtl design engineer in Cleveland, OH is $46.27, according to ZipRecruiter salary data. Most workers in this role earn between $23.56 and $59.90 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Cleveland, OH?

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Freelance Asic Rtl Design Engineer jobs near you
Infographic showing various Freelance Asic Rtl Design Engineer job openings in Cleveland, OH as of August 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 100% In-person job distribution, with an average salary of $96,236 per year, or $46.3 per hour.

Senior ASIC Design Engineer, Analog and Power, remote OK

Innovative Technology Company focused on Essential Industry Customers

Mentor, OH • Remote

$125K - $165K/yr

Full-time

Medical, Dental, Retirement, PTO

Posted 2 days ago

New

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Job description

Bleeding Edge Ohio Based Technology Firm, Newly Created Role, Tremendous Growth Opportunity: You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design, simulation, verification, and delivery of custom ASICs focused on power/voltage conversion, battery‐powered systems, and pure analog circuitry. This role also requires meaningful experience with solid‐state fabrication, semiconductor process flows, and device‐level considerations that directly influence analog/power IC performance.

Core Responsibilities

  • Analog & Power ASIC Design: Own full transistor-level lifecycle (architecture to tape-out) with required expertise in pure analog design. Design power conversion circuits—including buck/boost converters, charge pumps, battery management ICs, low/high-voltage stages, and switching/linear regulators.
  • IP Development: Develop analog/power IP blocks (biasing networks, references, amplifiers, drivers, protection circuits). Run SPICE, corner, Monte Carlo, aging, and reliability simulations.
  • Layout & Fab Interaction: Drive floorplanning, parasitic extraction, matching, and PDK usage. Integrate device physics, doping profiles, oxide variations, high-voltage structures, thermal behavior, and isolation (trench, SOI, guard rings). Evaluate process variation impacts on analog stability and noise.
  • Project Ownership: Act as the sole ASIC engineer leading technical strategy, cross-functional integration (PCB, packaging, test), and documentation.

Required Experience & Skills

  • Education & Experience: BS/MS in EE, CE, or Physics; 8+ years in transistor-level ASIC/Analog IC design as a sole project lead.
  • Pure Analog Expertise: deep experience in pure analog design—transistor-level design, compensation, stability, noise, and biasing—alongside power-conversion and battery-powered architectures.
  • Tools: Hands-on proficiency with Cadence (Virtuoso, Spectre, ADE).
  • Semiconductor Physics & Fab: Deep understanding of CMOS/BiCMOS flows, device physics, high-voltage structures, fabrication constraints (implantation, oxidation, lithography), and reliability (BTI, HCI, TDDB).

Preferred Qualifications

  • Silicon debug, bench validation, and lab bring-up experience.
  • Background in wearables, IoT, battery-powered embedded systems, or wide-bandgap devices (GaN, SiC).
  • Familiarity with mixed-signal verification methodologies.
  • BS or MS Degree in Electrical Engineering, Computer Engineering, Physics or a related area.

Very Competitive Compensation and Benefits, Call or Apply Today!

Note: we can consider on-site (relocation assistance is offered), hybrid or remote employees who can travel to HQ as needed.

Company Description

Recession Resistant Business Model, Our Systems Stabilize and Support Highly Available Applications. Using profits to build and design best of breed solutions for our customers in Essential and Other Industries. Collaborative-Team focused environment, History of Hiring very smart people with solid engineering skills, experience and education. Tech-Minded-Curious People, Terrific Culture, Competitive Salaries, Benefits, Equity