SoC Design Engineer
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Quick apply
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Quick apply
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
Santa Clara, CA · On-site
$110K - $140K/yr
Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications
San Jose, CA · On-site
$149K - $215K/yr
As a senior technical contributor, you will work closely with microarchitecture, SoC/full-chip, IP ... Develop and maintain design models and collateral required to integrate FPGA circuits and IP into ...
San Jose, CA · On-site
$149K - $215K/yr
As a senior technical contributor, you will work closely with microarchitecture, SoC/full-chip, IP ... Develop and maintain design models and collateral required to integrate FPGA circuits and IP into ...
San Jose, CA · On-site
$149K - $215K/yr
As a senior technical contributor, you will work closely with microarchitecture, SoC/full-chip, IP ... Develop and maintain design models and collateral required to integrate FPGA circuits and IP into ...
San Jose, CA · On-site
$149K - $215K/yr
As a senior technical contributor, you will work closely with microarchitecture, SoC/full-chip, IP ... Develop and maintain design models and collateral required to integrate FPGA circuits and IP into ...
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place ... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
San Jose, CA · On-site
$149K - $215K/yr
About the Role As a Sr. Debug Design Verification Engineer, you will be responsible for Design for ... SoC, FPGA & Full Chip design verification. * Create test case and testbench with UVM methodology ...
San Jose, CA · On-site
$149K - $215K/yr
About the Role As a Sr. Debug Design Verification Engineer, you will be responsible for Design for ... SoC, FPGA & Full Chip design verification. * Create test case and testbench with UVM methodology ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
... software engineering, and systems integration. www.tekwissen.com The position is for 1 ... Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's) Job Duty ...
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
Santa Clara, CA · On-site
$159K - $164K/yr
Description As a CPU Physical Design and Integration Engineer, you will be participating in the ... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.) * Deep expertise ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements ...
... integration. * Experience in one or more static timing tools (e.g., PrimeTime, Tempus ... Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements ...
$85K - $95.3K
1% of jobs
$95.3K - $105.6K
4% of jobs
$105.6K - $116K
6% of jobs
$116K - $126.3K
9% of jobs
$128.4K is the 25th percentile. Wages below this are outliers.
$126.3K - $136.6K
23% of jobs
The median wage is $141.4K / yr.
$136.6K - $146.9K
14% of jobs
$146.9K - $157.2K
10% of jobs
$163.2K is the 75th percentile. Wages above this are outliers.
$157.2K - $167.5K
14% of jobs
$167.5K - $177.9K
11% of jobs
$177.9K - $188.2K
5% of jobs
$188.2K - $198.5K
3% of jobs
$85K
$147.3K
$198.5K
For Fpga Full Chip Integration Engineer jobs, the most frequently searched job titles are:
Santa Clara, CA
$110K - $140K/yr
Full-time
Re-posted 8 days ago
Sourced by ZipRecruiter
Software development
1,001 - 5,000 Employees
Santa Clara, CA, US
1995