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Fpga Full Chip Integration Engineer Jobs (NOW HIRING)

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Full-chip integration and verification * Chip bring-up, validation, and debugging * Participate in the FPGA development * Architecture, registers, interface and design documentation. Qualifications

As a senior technical contributor, you will work closely with microarchitecture, SoC/full-chip, IP ... Develop and maintain design models and collateral required to integrate FPGA circuits and IP into ...

About the Role As a Sr. Debug Design Verification Engineer, you will be responsible for Design for ... SoC, FPGA & Full Chip design verification. * Create test case and testbench with UVM methodology ...

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Fpga Full Chip Integration Engineer information

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$85K

$147.3K

$198.5K

How much do fpga full chip integration engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for fpga full chip integration engineer in the United States is $147,315.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,000.00 and $167,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Fpga Full Chip Integration Engineer jobs?

For Fpga Full Chip Integration Engineer jobs, the most frequently searched job titles are:

SoC Design Engineer

Santa Clara, CA

OMNIVISION
Software Development • 1 - 5K employees

$110K - $140K/yr

Full-time

Re-posted 8 days ago


Job description

Responsibilities :
  • Image sensor control or processing function design and verification
  • High speed interface (USB/MIPI) design and verification
  • Full-chip integration and verification
  • Chip bring-up, validation, and debugging
  • Participate in the FPGA development
  • Architecture, registers, interface and design documentation.            
Qualifications :
  • PhD or MSEE with some experience of digital design 
  • Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality
  • Knowledge of high performance and low power design techniques.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of SOC architecture.
  • Knowledge of assertion-based formal verification is a plus
  • Image processing/DSP knowledge is a plus
Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
EOE/Minorities/Females/Vet/Disability