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Formal Verification Jobs in Texas (NOW HIRING)

Custom Timing and Verification CAD Engineer

Austin, TX

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Custom Timing and Verification CAD Engineer

Austin, TX

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Hardware Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Experience with formal verification techniques, emulation platforms is a plus * Excellent problem-solving skills and attention to detail * Strong communication and collaboration skills rich.goldstein ...

Senior Verification Engineer

Austin, TX

$103K - $142K/yr

... SVA) Apply formal verification methodologies Demonstrate strong debugging skills, including failure reproduction and root-cause analysis Exhibit strong analytical and problem-solving skills ...

Custom Timing and Verification CAD Engineer

Austin, TX

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress ...

Apply formal verification and emulation techniques to complement simulation-based approaches and improve verification efficiency * Collaborate with design, architecture, and post-silicon validation ...

Custom Timing and Verification CAD Engineer

Austin, TX

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Custom Timing and Verification CAD Engineer

Austin, TX

$129K - $194K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Formal Property Verification, Proof Kits. * Experience leading a technical team, including mentoring, training, and performing technical peer reviews. * Embedded programming for ARM, or GPU ...

Custom Timing and Verification CAD Engineer

Austin, TX

$129K - $194K/yr

  • Medical

  • Dental

  • Retirement

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom ...

Showing results 41-60

Formal Verification information

What is a formal verification?

A Formal Verification job involves using mathematical techniques to prove the correctness of hardware or software designs. Engineers in this role apply formal methods, such as model checking and theorem proving, to ensure that a system behaves as intended without relying solely on traditional testing. This process helps detect critical design flaws early, improving reliability and reducing costly errors. Formal verification is widely used in safety-critical industries like aerospace, automotive, and semiconductor design.

How to become a formal verification engineer?

To become a formal verification engineer, typically a candidate needs a bachelor's degree in electrical engineering, computer engineering, or computer science. Strong skills in hardware description languages like VHDL or Verilog, knowledge of formal methods and model checking tools, and experience with scripting languages such as Python are important. Gaining hands-on experience through internships or projects and obtaining relevant certifications can also enhance job prospects.

What skills and qualifications are needed for formal verification?

To thrive in Formal Verification, you need a strong background in computer science, mathematics, and logical reasoning, often supported by a relevant degree in engineering or computer science. Familiarity with formal verification tools such as ModelSim, JasperGold, SystemVerilog Assertions, and proficiency in hardware description languages like Verilog or VHDL are important, and industry certifications can be a plus. Excellent analytical thinking, attention to detail, and strong communication skills help in interpreting specifications and collaborating with cross-functional teams. These skills are crucial to rigorously ensuring hardware or software designs function correctly and meet industry safety and correctness standards.

What does a formal verification engineer do?

A Formal Verification engineer's daily responsibilities usually include developing and applying formal models to hardware or software designs, writing assertions, and using verification tools to prove or disprove correctness properties. Collaboration with design, simulation, and verification teams is common to clarify specifications and address any verification gaps. Engineers frequently analyze failures or counterexamples, document findings, and suggest design improvements. This role often involves balancing multiple projects, staying aligned with tight development schedules, and ensuring the highest possible design quality before production.

What are the most commonly searched types of Formal Verification jobs in Texas?

The most popular types of Formal Verification jobs in Texas are:

What cities in Texas are hiring for Formal Verification jobs?

Cities in Texas with the most Formal Verification job openings:

Infographic showing various Formal Verification job openings in Texas as of August 2026, with employment types broken down into 1% As Needed, 81% Full Time, 14% Part Time, and 4% Contract. Highlights an 91% Physical, 2% Hybrid, and 7% Remote job distribution.

ASIC Design Verification Engineer

Advanced Micro Devices, Inc

Austin, TX • On-site

Full-time

Re-posted 6 days ago


Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

27th of 157 rated electronics manufacturers


Job description


WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  



The Role:  

The MSIP UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge DDR technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off. You will be taking part in key technical leadership activities and collaborating with DV Architects and DV leads in shaping cutting verification environments for current and future programs.

As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person:

Strong analytical thinking and problem-solving skills, excellent attention to detail.

Possesses good teamwork, communication and interpersonal skills

A self-starter and able to independently drive tasks to completion

Enjoy working in a fast-paced, multi-project team environment using state-of-the-art tools and technology

Possesses a continuous improvement mind-set

Key Responsibilities:

  • Collaborate with IP architects to come up with verification architecture, verification methodology, improvements, and development plans
  • Taking on some key technical leadership responsibilities to help current DV leads and DV Architects
  • Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects
  • Work on test plans, verification environment development, regression, and coverage closure
  • Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC
  • Triaging and Debugging Regressions
  • Analyzing code and functional coverage
  • Deploying industry-leading verification methodologies such as UVM and formal Verification
  • Reproducing functional bugs found in post-silicon in dynamic simulation and/or formal verification environments
  • Conducting and participating in code reviews
  • Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution

Preferred Experience:

  • ASIC verification experience
  • Strong understanding of digital design and computer architecture
  • Strong understanding and experience in block-level constrained random verification
  • Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments
  • ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools
  • Experience in formal verification would be an asset

Academic Credentials:

  • BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

This role is not eligible for visa sponsorship.

#LI-DP1



Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Qualifications:

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Education:UNAVAILABLEEmployment Type: FULL_TIME

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