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Flip Chip Jobs (NOW HIRING)

Aziro Technologies LLC

IC Packaging Engineer

San Jose, CA

$159.40K/yr

Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe) * Strong understanding of electrical, mechanical, thermal, and ...

Paradromics

Senior Microelectronics Process Engineer

Austin, TX · On-site

$103.10K - $133.30K/yr

Own and maintain in-house backend microfabrication and microelectronics assembly processes, including wire bonding, flip chip bonding, solder bumping, underfill/epoxy dispensing, reflow, and related ...

Apple

Package Integration Engineer

San Francisco, CA · On-site

$122.50K - $164.90K/yr

Some hands-on knowledge in Wafer Bumping, Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach (including multilayer thin die stacking), encapsulation ...

Neuralink

Manufacturing Technician

Austin, TX · On-site

$25 - $31/hr

Operate equipment, such as flip-chip bonders and laser welders * Execute equipment maintenance and calibration * Package final products for delivery * Maintain parts inventory * Run functional ...

Altera

Senior OSAT Engineer

San Jose, CA

$159.70K - $231K/yr

Optimize packaging and test architectures for performance, cost, and reliability: flip-chip BGA, high-pin-count packages, substrate technologies, wafer-level solutions, burn-in/FT coverage. * Monitor ...

Qualcomm

Staff Packaging Engineer

San Diego, CA · On-site

Extensive expertise in Flip Chip, Wire Bond, and System in Package (SiP) assembly processes, as well as familiarity with related materials and equipment, is required. The role demands strong ...

Teledyne

Focal Plane Engineer

Camarillo, CA · On-site

$141.90K - $189.20K/yr

Collaborate with diverse teams in crystal material growth, array detector fabrication, flip-chip hybridization, sensor assembly and performance testing to leverage existing or emerging design and ...

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Flip Chip information

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How much do flip chip jobs pay per year?

As of May 29, 2026, the average yearly pay for flip chip in the United States is $135,650.00, according to ZipRecruiter salary data. Most workers in this role earn between $108,500.00 and $184,000.00 per year, depending on experience, location, and employer.

What is a Flip Chip job?

A Flip Chip job typically involves working with advanced semiconductor packaging technology, where components are flipped and directly bonded to a substrate or circuit board. Responsibilities may include operating equipment, inspecting wafer bonding, troubleshooting defects, and ensuring quality control. Workers in this role are often found in semiconductor manufacturing and may need experience with cleanroom environments, precision tools, and microscopy techniques.

What are the key skills and qualifications needed to thrive in the Flip Chip position, and why are they important?

To thrive in a Flip Chip process engineering role, you need a strong understanding of semiconductor packaging, microelectronics assembly, and materials science, often supported by a degree in electrical engineering, materials science, or a related field. Experience with tools such as wire bonders, die attachers, flip chip bonders, and knowledge of cleanroom protocols and industry standards like IPC is highly valuable. Attention to detail, problem-solving ability, and excellent teamwork are crucial soft skills for this position. These competencies ensure successful assembly, reliability, and performance of advanced semiconductor devices in a fast-paced and precise manufacturing environment.

What are common challenges faced in a Flip Chip engineering role?

One of the main challenges in a Flip Chip process engineering position is maintaining high yields and reliability while working with ever-decreasing component sizes and complex assembly processes. Engineers must troubleshoot defects, optimize process parameters, and stay updated with evolving industry technologies. The role often involves cross-functional collaboration with design, quality, and production teams to ensure product integrity. Overcoming these challenges helps build expertise in advanced microelectronic packaging and can position you for advancement within the semiconductor manufacturing industry.
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Flip Chip jobs near you
Infographic showing various Flip Chip job openings in the United States as of May 2026, with employment types broken down into 1% Internship, 1% As Needed, 64% Full Time, 31% Part Time, 1% Temporary, and 2% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $135,650 per year, or $65.2 per hour.

IC Packaging Engineer

Aziro Technologies LLC

San Jose, CA

$159.40K/yr

Other

Posted 18 days ago

Job description

Job Description

Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.

You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.

Key Responsibilities

  • Serve as technical authority for IC and SiP packaging across multiple products and programs.
  • Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
  • Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
  • Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces.
  • Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
  • Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels.
  • Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
  • Influence product roadmap, risk management, and investment decisions through technical insight.
  • Establish scalable design methodologies, best practices, and reusable packaging flows.

Qualifications

  • BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field.
  • Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products.
  • Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)
  • Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimization
  • Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment.

Required Experience

  • Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production.
  • Proven experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5 / LPDDR5X, USB 3.x or 10G interfaces
  • Experience defining die-to-die and chiplet based RDL/bump architecture.
  • Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
  • Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams.
  • Clear understanding of cost, yield, schedule, and risk trade-offs at a product and portfolio level.

Tools & Preferred Skills

  • Cadence Allegro Package Designer (APD) or equivalent EDA tools.
  • Strong background in flip-chip BGA package design and layout.
  • SI/PI expertise preferred, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
  • Experience building new packaging methodologies or platforms from scratch.

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