Job Summary:
Cadence is a technology company focused on innovation and leadership. They are seeking an experienced C++ software engineer to develop and enhance their FPGA-Based Prototyping product, working with a team to improve the Protium Timing flow and develop new algorithms for quality of results and performance.
Responsibilities:
• Enhance and support Timing Engine to add new features and extend existing features
• Enhance and support Timing Flow to improve P&R compile time
• The role involves designing, tuning, and innovating timing graph algorithms and flow operating on multi‑billion‑node timing graphs
• Write Specifications and Unit Tests for your code
Qualifications:
Required:
• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Experience in EDA software development.
• Strong background in SDC constraints and Timing Analysis
• Excellent programming skills in C/C++
Preferred:
• Strong knowledge of Tcl
• Experience in multi-threaded/ concurrent programming
• Prior experience with Emulation or FPGA software development
Company:
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Founded in 1988, the company is headquartered in San Jose, USA, with a team of 10001+ employees. The company is currently Late Stage.