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Eda Verification Engineer Jobs (NOW HIRING)

Apple

Formal Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$184K - $324K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$184K - $324K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX

$184K - $324K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

Description As a formal verification engineer working the complete formal verification for single ... Experience in using EDA formal tools and tool development experience is plus. Proficiency in any ...

Apple

Formal Verification - AI/ML Engineer

Austin, TX · On-site

$184K - $324K/yr

You will work closely with formal verification engineers, design engineers, and EDA tool developers to identify high-impact opportunities and deliver practical, domain-specific AI applications.

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Eda Verification Engineer information

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$80K

$142.6K

$203.5K

How much do eda verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for eda verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is an EDA Verification Engineer?

An EDA Verification Engineer is a professional who uses Electronic Design Automation (EDA) tools to verify the functionality and correctness of integrated circuit (IC) designs before manufacturing. Their primary responsibility is to ensure that the design meets all specifications and works as intended by developing and running simulation tests and debugging issues. They work closely with design engineers, write testbenches, and use verification methodologies such as UVM (Universal Verification Methodology). This role is critical in preventing costly design errors and ensuring high-quality semiconductor products.

How does an EDA Verification Engineer typically collaborate with design and software teams during the verification process?

As an EDA Verification Engineer, you'll work closely with both design and software teams to ensure that integrated circuits or electronic systems meet their specifications. Collaboration involves frequent communication to clarify design intent, align on test coverage goals, and resolve bugs. You'll participate in regular meetings, share verification plans, and provide feedback on design changes, often using shared project management tools and version control systems. This cross-functional teamwork is essential for identifying potential issues early and ensuring a high-quality final product.

What are the key skills and qualifications needed to thrive as an EDA Verification Engineer, and why are they important?

To thrive as an EDA Verification Engineer, you need a solid background in digital design, verification methodologies (like UVM or SystemVerilog), and a degree in electrical engineering or a related field. Familiarity with simulation tools (such as Cadence or Synopsys), scripting languages (Python, Perl), and version control systems is typically required. Strong analytical thinking, attention to detail, and effective teamwork are soft skills that set top performers apart. These skills ensure the accurate validation of complex integrated circuits, reducing design errors and enabling successful product launches.

What are popular job titles related to Eda Verification Engineer jobs?

For Eda Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Eda Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 97% Full Time, and 2% Part Time. Highlights an 91% Physical, 4% Hybrid, and 5% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Verification Platform Engineer, Platform Architecture

Austin, TX • On-site

Socket.dev
Network Security • 1 - 10 employees
Learn more about Socket.devexternal

$134K/yr

Other

Posted 8 days ago

Job description

Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.

Description

This role bridges Apple's next-generation platform technology with DV methodology and tooling. We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.

Minimum Qualifications
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
  • Experience with SystemVerilog and EDA tooling.
  • Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
Preferred Qualifications
  • Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
  • 3+ years of relevant experience.
  • Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
  • Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
  • Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
  • Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.
  • Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
  • Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.
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