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Eda Engineer Jobs (NOW HIRING)

Neurophos Inc

CAD/EDA Manager

San Jose, CA · On-site

$220K - $255K/yr

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable ... Key Responsibilities EDA Tool and Flow Management * Evaluate, deploy, and support EDA tools ...

Rivian

Automation Engineer, EDA

Palo Alto, CA · On-site

$103K - $115K/yr

As an Automation Engineer, EDA (Electronic Design Automation), you will bridge the gap between software development and hardware design. Focused on the Cadence Allegro X ecosystem and Altium, you ...

Rivian

Automation Engineer, EDA

Palo Alto, CA · On-site

$103K - $115K/yr

As an Automation Engineer, EDA (Electronic Design Automation), you will bridge the gap between software development and hardware design. Focused on the Cadence Allegro X ecosystem and Altium, you ...

OMNIVISION

Sr. EDA Flow Engineer

Santa Clara, CA · On-site

$110K - $145K/yr

Hands-on experience applying machine learning to real-world engineering problems * Solid understanding of at least one major EDA workflow domain (e.g., place & route, physical layout, DRC/LVS, STA ...

Nvidia Corporation

EDA License Engineer

Santa Clara, CA · On-site

$96K - $129K/yr

As an EDA License Engineer at NVIDIA, you will play a crucial role in managing and optimizing our engineering software licenses. This position offers an outstanding opportunity to collaborate with ...

Nvidia

EDA License Engineer

Santa Clara, CA · Hybrid

$96K - $129K/yr

As an EDA License Engineer at NVIDIA, you will play a crucial role in managing and optimizing our engineering software licenses. This position offers an outstanding opportunity to collaborate with ...

Intel

EDA Tools Hardware Engineer

Austin, TX

$141K - $269K/yr

We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files ...

Intel

EDA Tools Hardware Engineer

Santa Clara, CA

$141K - $269K/yr

We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files ...

Tensordyne

Sr. ASIC EDA Workflow Engineer

Sunnyvale, CA · On-site

In this hands-on, technology leadership role, you will lead EDA tool flow management, and associated engineering workflow development for Tensordyne's multimodal generative AI inference acceleration ...

Intel

EDA Tools Hardware Engineer

Hillsboro, OR

$141K - $269K/yr

We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files ...

Tensordyne

Sr. ASIC EDA Workflow Engineer

Sunnyvale, CA · On-site +1

In this hands-on, technology leadership role, you will lead EDA tool flow management, and associated engineering workflow development for Tensordyne's multimodal generative AI inference acceleration ...

Intel

EDA Tools Hardware Engineer

Folsom, CA

$141K - $269K/yr

We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files ...

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Eda Engineer information

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$33K

$89.2K

$142K

How much do eda engineer jobs pay per year?

As of Jul 12, 2026, the average yearly pay for eda engineer in the United States is $89,183.00, according to ZipRecruiter salary data. Most workers in this role earn between $66,500.00 and $109,000.00 per year, depending on experience, location, and employer.

What are EDA engineers?

EDA engineers, or Electronic Design Automation engineers, are professionals who develop and use software tools to design, simulate, and verify electronic systems and integrated circuits. They work closely with hardware designers to optimize circuits for performance, power, and area, ensuring manufacturability and reliability. EDA engineers often write scripts, develop custom tools, and troubleshoot issues throughout the design process. Their expertise is essential in the semiconductor industry, enabling the creation of complex chips found in modern electronics.

What are the key skills and qualifications needed to thrive as an EDA Engineer, and why are they important?

To thrive as an EDA Engineer, you need a solid background in electrical engineering, computer science, or a related field, with expertise in digital or analog circuit design. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, as well as proficiency in scripting languages such as Python or TCL, is typically required. Strong problem-solving skills, attention to detail, and effective communication are important soft skills for collaborating with design teams and troubleshooting complex issues. These skills and qualifications are crucial for ensuring efficient and accurate design automation, leading to successful chip development and faster time-to-market.

What is the difference between Eda Engineer vs PCB Design Engineer?

AspectEda EngineerPCB Design Engineer
CredentialsBachelor's in Electrical Engineering or related; knowledge of EDA toolsBachelor's in Electrical Engineering, Electronics, or related; proficiency in PCB design software
Work EnvironmentDesign teams, electronics manufacturing, R&D labsElectronics companies, manufacturing, prototyping labs
Industry UsageUsed across electronics, semiconductor, and hardware industriesPrimarily in electronics hardware and PCB manufacturing sectors
Job FocusDesigning, verifying, and optimizing electronic circuits using EDA toolsCreating detailed PCB layouts and ensuring manufacturability

While both roles involve electronic design, Eda Engineers focus on circuit design and verification using EDA tools, whereas PCB Design Engineers specialize in laying out printed circuit boards for manufacturing. Both roles require similar educational backgrounds and often collaborate in electronics development projects.

What are some common challenges EDA Engineers face when working on complex chip designs, and how can they overcome them?

EDA Engineers often encounter challenges such as managing large-scale design data, optimizing for timing and power constraints, and debugging intricate tool flows. Navigating frequent changes in design specifications and collaborating with cross-functional teams can also be demanding. To overcome these hurdles, EDA Engineers should stay up-to-date with the latest tool advancements, maintain clear communication with hardware and verification teams, and develop strong problem-solving skills to efficiently debug and optimize designs. Leveraging automation and scripting can also help streamline repetitive tasks.
More about Eda Engineer jobs
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Eda Engineer jobs near you
Infographic showing various Eda Engineer job openings in the United States as of July 2026, with employment types broken down into 6% As Needed, 89% Full Time, 2% Part Time, and 3% Contract. Highlights an 89% Physical, 4% Hybrid, and 7% Remote job distribution, with an average salary of $89,183 per year, or $42.9 per hour.
CAD/EDA Manager

CAD/EDA Manager

Neurophos Inc

San Jose, CA • On-site

$220K - $255K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 3 days ago

Job description

About Neurophos
The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn't about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn't going to meet the need, so we took a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We've assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft's Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of computing!
Position Overview
We are seeking an experienced CAD Manager to lead and manage the EDA tooling, design flows, and physical design infrastructure for our analog and mixed-signal IC design teams. In this role, you will be responsible for evaluating and deploying EDA tools, developing robust custom flows from schematic capture through tape-out, and ensuring maximum designer productivity across multiple process nodes. You will work closely with design, verification, and process engineering teams to solve the toughest implementation challenges in advanced analog design.
Location
Austin, TX or San Jose, CA. Full-time onsite position.
Key Responsibilities
EDA Tool and Flow Management
  • Evaluate, deploy, and support EDA tools, including Cadence Virtuoso, Spectre, Calibre, and related analog/custom IC toolsets.
  • Develop, maintain, and optimize design flows for schematic entry, simulation, layout, parasitic extraction (PEX), and physical verification (DRC/LVS).
  • Manage EDA tool licenses, vendor relationships, and tool upgrade cycles to ensure the design team's productivity.
  • Implement and maintain PDK installations and updates, coordinating with foundry partners (including TSMC) for process node enablement, with specific focus on advanced technology qualification and ramp.
  • Lead CAD enablement for TSMC N3P and N2P advanced nodes, including PDK bring-up, design rule updates, fill strategy, and integration / sign-off flow alignment with TSMC requirements.
  • Interface with foundries and VCA partners to facilitate a smooth tape-out process.

Infrastructure and Automation
  • Architect and maintain the CAD computing environment, including Linux workstations, EDA servers, and LSF/grid computing clusters.
  • Develop and maintain SKILL, Tcl, Python, and shell scripts to automate repetitive CAD tasks and streamline designer workflows.
  • Manage design data integrity through version control systems (Git, Vault, ClearCase) and define backup and archive strategies.
  • Collaborate with IT to plan compute resource needs, capacity planning, and infrastructure upgrades.

Team Leadership and Collaboration
  • Act as the primary technical liaison between design teams, foundries, and EDA vendors.
  • Define and enforce CAD best practices, design methodology guidelines, and tape-out checklists.
  • Provide hands-on debug support for flow and tool issues during critical project phases and tape-out windows.
  • Drive continuous improvement initiatives to reduce design cycle time and improve first-pass silicon success rates.

Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a closely related field.
  • 8+ years of hands-on experience in analog/mixed-signal IC CAD or EDA engineering.
  • Deep expertise in Cadence Virtuoso suite (schematic, layout, ADE), Spectre/Spectre X simulation, and Cadence Virtuoso SKILL scripting.
  • Strong knowledge of physical verification tools: Mentor Calibre (DRC, LVS, PEX) and/or Synopsys IC Validator.
  • Proven experience with PDK integration and support for advanced CMOS nodes; hands-on experience with TSMC N3P and/or N2P process nodes strongly preferred.
  • Familiarity with TSMC design rule documents (DRM), analog design guidelines (ADG), and tape-out sign-off requirements for N3P/N2P.
  • Proficiency in at least two scripting languages: Python, SKILL, Tcl, or Perl.
  • Experience managing EDA tool licensing (FlexLM/RLM) and floating license optimization.
  • Strong understanding of Linux/Unix computing environments and HPC cluster management.

Preferred Skills
  • Experience with custom digital/mixed-signal flows, including OpenAccess, Virtuoso Layout Suite XL, or Virtuoso RF.
  • Familiarity with post-layout simulation (EMIR, noise, reliability) methodologies.
  • Knowledge of EM/IR analysis tools (Voltus, RedHawk) applied to analog/custom blocks.
  • Prior people management or technical lead experience in a tape-out-oriented environment.
  • Experience with high-speed I/O, SerDes, PLLs, or RF circuit design CAD flows.
  • Familiarity with configuration management tools and agile project tracking (SOS, JIRA, Confluence).

What We Offer
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You'll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Benefits
Join a team that invests in your future and your well-being. At Neurophos, we offer:
  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
  • Unlimited PTO. No rigid vacation banks, just a focus on delivery.
  • 401(k) matching and stock option opportunities to ensure our success is your success.
  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
  • Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don't.

Apply