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Dft Manager Jobs in Massachusetts (NOW HIRING)

Apple Inc.

SoC DFT DV Engineer

Waltham, MA · On-site

$140 - $190/hr

Experience working under strict schedule deadlines with the ability to manage multiple priorities * Ability to lead project executionGood knowledge of general logic design, and exposure to DFT is a ...

New

SES

Technical Product Manager

Woburn, MA

$200K - $225K/yr

Bridge scientific research and engineering by defining how scientific findings (e.g., from DFT/MD ... Product Management Experience: Proven experience as a Science-literate Product Manager overseeing ...

SES

Computational Materials Scientist

Woburn, MA

$180K - $200K/yr

Conduct and oversee DFT (Density Functional Theory), MD (Molecular Dynamics), and QM (Quantum ... manage and analyze large datasets. Education and/or Experience: * Education: Ph.D. in Mechanical ...

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Dft Manager information

See Massachusetts salary details

$31.1K

$68.4K

$124K

How much do dft manager jobs pay per year?

As of Sep 2, 2026, the average yearly pay for dft manager in Massachusetts is $68,434.00, according to ZipRecruiter salary data. Most workers in this role earn between $49,100.00 and $75,400.00 per year, depending on experience, location, and employer.

What is a DFT manager?

DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.

What are the key skills and qualifications needed to thrive as a DFT manager?

To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.

What are some common challenges a DFT manager faces when coordinating between design and test teams?

A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.

What is the difference between Dft Manager vs Dft Engineer?

AspectDft ManagerDft Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniquesBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools
Work EnvironmentOversees DFT teams, manages testing strategies, collaborates with design and manufacturingPerforms DFT design, implements test structures, analyzes test data
Industry UsageUsed in semiconductor and integrated circuit industries for testability managementUsed in semiconductor design for implementing testability features

The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.

What are the most commonly searched types of Dft jobs in Massachusetts?

The most popular types of Dft jobs in Massachusetts are:

What are popular job titles related to Dft Manager jobs in Massachusetts?

For Dft Manager jobs in Massachusetts, the most frequently searched job titles are:

What job categories do people searching Dft Manager jobs in Massachusetts look for?

The top searched job categories for Dft Manager jobs in Massachusetts are:

What cities in Massachusetts are hiring for Dft Manager jobs?

Cities in Massachusetts with the most Dft Manager job openings:

Dft Manager jobs near you
Infographic showing various Dft Manager job openings in Massachusetts as of August 2026, with employment types broken down into 1% As Needed, 87% Full Time, 11% Part Time, and 1% Contract. Highlights an 93% Physical, 3% Hybrid, and 4% Remote job distribution, with an average salary of $68,434 per year, or $32.9 per hour.

Sr. Design for Test (DFT) Engineer

Lightmatter

Boston, MA • On-site

Full-time

Re-posted 7 days ago

Job description

 As a Design for Test Engineer you will work closely with all disciplines involved in chip design and product operations to design, validate, and deploy test solutions for digital, analog, and photonic logic. You will be involved in a variety of tasks including logic design, validation and logic simulations, scripting, timing closure, post-silicon planning and bring up, and bringing products to market.

Responsibilities

  • Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform
  • Develop and deploy DFT methodologies for our next generation products
  • Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan
  • Work with RTL designers to define front-end integration
  • Work with physical-design engineers to provide backend integration
  • Create automated flow that can scale with the team and company
  • Support initial silicon bring-up through debug 
  • Validate DFT implementation and requirements
  • Proactively solve problems while managing deliverables in a fast-paced, evolving environment.

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs
  • Proven experience in pre-silicon design activities
  • Work independently on daily tasks and projects, while seeking guidance for new and unfamiliar assignments.
  • Experience with scripting languages such as Python or TCL
  • Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG
  • Knowledge of Basic SoC Architecture and HDL languages like Verilog
  • Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan. 

Preferred Qualifications:

  • Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts
  • Prior experience working on DFT related tasks in either logic design, validation, implementation or pattern generation and coverage analysis
  • Understanding of industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST, and trade-offs between test quality and test time
  • Ability to conduct experiments during silicon debug, gathering and analyzing data, and utilize scripting to support efficient handling of ATE data 
  • Understanding of Timing, Physical Design, and Power impact of DFT structures
  • Strong teamwork and communication skills with the ability to collaborate with multiple functional teams across a variety of fields

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