DFT Architect
San Jose, CA · On-site
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
DFT Architect TylSemi, Inc. San Jose, California, United States About this position About TylSemi, Inc. The Opportunity The Opportunity The AI infrastructure market is exploding. Every hyperscaler ...
San Jose, CA · On-site
DFT Architect TylSemi, Inc. San Jose, California, United States About this position About TylSemi, Inc. The Opportunity The Opportunity The AI infrastructure market is exploding. Every hyperscaler ...
San Jose, CA · On-site
$203K/yr
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
$203K/yr
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...
San Jose, CA · On-site
$209K - $299K/yr
About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next‑generation DFT architecture across Altera's most advanced FPGA, SoC ...
San Jose, CA · On-site
$209K - $299K/yr
About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next‑generation DFT architecture across Altera's most advanced FPGA, SoC ...
San Jose, CA · On-site
$209K - $299K/yr
About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera's most advanced FPGA, SoC ...
San Jose, CA · On-site
$209K - $299K/yr
About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera's most advanced FPGA, SoC ...
San Jose, CA · On-site
$237K - $286K/yr
Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs. * Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression ...
San Jose, CA · On-site
$237K - $286K/yr
Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs. * Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression ...
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high ...
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high ...
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high ...
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high ...
Responsibilities include implementing and optimizing DFT architectures and collaborating with teams across firmware, architecture, and design. The ideal candidate has at least 5 years of experience ...
Responsibilities include implementing and optimizing DFT architectures and collaborating with teams across firmware, architecture, and design. The ideal candidate has at least 5 years of experience ...
Plano, TX · Remote
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ...
Quick apply
Plano, TX · Remote
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ...
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
Santa Clara, CA · On-site
Work on Scan insertion, ATPG, GLS (timing/non-timing) Implement MBIST and/or Boundary Scan (BSCAN, JTAG) Support DFT architecture and chip-level integration Debug DFT issues and improve test coverage ...
Quick apply
Santa Clara, CA · On-site
Work on Scan insertion, ATPG, GLS (timing/non-timing) Implement MBIST and/or Boundary Scan (BSCAN, JTAG) Support DFT architecture and chip-level integration Debug DFT issues and improve test coverage ...
Plano, TX · Remote
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ...
Quick apply
Plano, TX · Remote
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ...
San Jose, CA · On-site
$144K - $191K/yr
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows. * Experience with industry-leading EDA tools for ...
Quick apply
San Jose, CA · On-site
$144K - $191K/yr
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows. * Experience with industry-leading EDA tools for ...
San Jose, CA · On-site
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows. * Experience with industry-leading EDA tools for ...
Quick apply
San Jose, CA · On-site
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows. * Experience with industry-leading EDA tools for ...
Irvine, CA · On-site
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
Quick apply
Irvine, CA · On-site
This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross ...
San Jose, CA · On-site
DFT Architecture definition. - Must Full chip / Sub system level DFT activities - Must Scan & compression (EDT) implementation LBIST implementation and verification - any BIST exp Coverage ...
Quick apply
San Jose, CA · On-site
DFT Architecture definition. - Must Full chip / Sub system level DFT activities - Must Scan & compression (EDT) implementation LBIST implementation and verification - any BIST exp Coverage ...
Austin, TX · On-site
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
Austin, TX · On-site
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
San Jose, CA · On-site
DFT Architecture & Integration: Responsible for top-level DFT planning and integration. * ATPG & ATE: Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment ...
San Jose, CA · On-site
DFT Architecture & Integration: Responsible for top-level DFT planning and integration. * ATPG & ATE: Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment ...
States with the most job openings for Dft Architect jobs include:
For Dft Architect jobs, the most frequently searched job titles are:

San Jose, CA • On-site
Full-time
Re-posted 9 days ago
8.6
Based on 13 frontline employees who took The Breakroom Quiz
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT architect is expected to apply past technical knowledge, learn new cutting-edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT architect will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high-volume production.
THE PERSON:
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION:
San Jose, California, United States
This role is not eligible for visa sponsorship.
#LI-AJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEGet the full story on Breakroom
Sourced by ZipRecruiter
Computer and electronic product manufacturing and manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US