DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Staff FPGA Design Engineer
Irvine, CA · On-site
$132K - $181K/yr
This role owns FPGA RTL design from concept through qualification, integration, and mission operations. The engineer collaborates across avionics, embedded software, systems, and hardware teams to ...
Staff FPGA Design Engineer
Irvine, CA · On-site
$132K - $181K/yr
This role owns FPGA RTL design from concept through qualification, integration, and mission operations. The engineer collaborates across avionics, embedded software, systems, and hardware teams to ...
Digital Design Lead
Irvine, CA · On-site
$180K - $200K/yr
Mentor junior design engineers and coordinate with verification, DFT, and physical design teams to meet project schedules. Required Skills & Experience * Proven track record as an RTL Design Lead on ...
Digital Design Lead
Irvine, CA · On-site
$180K - $200K/yr
Mentor junior design engineers and coordinate with verification, DFT, and physical design teams to meet project schedules. Required Skills & Experience * Proven track record as an RTL Design Lead on ...
Senior FPGA Design Engineer job opportunity at Fullerton, CA
Fullerton, CA · On-site
$113.63/hr
... RTL design and implementation in VHDL or Verilog - Timing analysis and closure on high‑speed ... multidisciplinary engineering teams Required Qualifications - Active Secret clearance at start ...
Quick apply
Senior FPGA Design Engineer job opportunity at Fullerton, CA
Fullerton, CA · On-site
$113.63/hr
... RTL design and implementation in VHDL or Verilog - Timing analysis and closure on high‑speed ... multidisciplinary engineering teams Required Qualifications - Active Secret clearance at start ...
Senior FPGA Design Engineer job opportunity at Fullerton, CA with Security Clearance
Fullerton, CA · On-site
$113.63/hr
... RTL design and implementation in VHDL or Verilog - Timing analysis and closure on high‑speed ... multidisciplinary engineering teams Required Qualifications - Active Secret clearance at start ...
Senior FPGA Design Engineer job opportunity at Fullerton, CA with Security Clearance
Fullerton, CA · On-site
$113.63/hr
... RTL design and implementation in VHDL or Verilog - Timing analysis and closure on high‑speed ... multidisciplinary engineering teams Required Qualifications - Active Secret clearance at start ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
We're hiring: Senior Hardware Design Engineer (Irvine, CA, Hybrid) Work on technology at the ... RTL implementation (Verilog/SystemVerilog) for complex ASIC/FPGA products * Full design flow ...
We're hiring: Senior Hardware Design Engineer (Irvine, CA, Hybrid) Work on technology at the ... RTL implementation (Verilog/SystemVerilog) for complex ASIC/FPGA products * Full design flow ...
DDR Design Engineer
Irvine, CA · On-site
$175K - $308K/yr
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
$175K - $308K/yr
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
$122K - $214K/yr
You will provide high-quality RTL description, including assertions, for the design. Use formal ... Electrical Engineering. Pay & Benefits At Apple, base pay is one part of our total compensation ...
DDR Design Engineer
Irvine, CA · On-site
$122K - $214K/yr
You will provide high-quality RTL description, including assertions, for the design. Use formal ... Electrical Engineering. Pay & Benefits At Apple, base pay is one part of our total compensation ...
FPGA Design Engineer
Los Angeles, CA · On-site
$100K - $140K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
FPGA Design Engineer
Los Angeles, CA · On-site
$100K - $140K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$132K - $182K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$132K - $182K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
ASIC Design Engineer - DSP / Analog / SerDes
Irvine, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Perform RTL simulation and debugging to ensure design functionality and performance. Contribute to ...
ASIC Design Engineer - DSP / Analog / SerDes
Irvine, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Perform RTL simulation and debugging to ensure design functionality and performance. Contribute to ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
FPGA Engineer with Security Clearance
El Segundo, CA · On-site
$131K - $180K/yr
... RTL design, verification, and lab integration. Key Responsibilities Design & Architecture ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
FPGA Engineer with Security Clearance
El Segundo, CA · On-site
$131K - $180K/yr
... RTL design, verification, and lab integration. Key Responsibilities Design & Architecture ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
Los Angeles, CA · On-site
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Cpu Rtl Design Engineer information
See Los Angeles, CA salary details
$43.6K - $55.2K
2% of jobs
$55.2K - $66.8K
11% of jobs
$72.9K is the 25th percentile. Wages below this are outliers.
$66.8K - $78.3K
23% of jobs
The median wage is $85.7K / yr.
$78.3K - $89.9K
22% of jobs
$89.9K - $101.4K
17% of jobs
$101.8K is the 75th percentile. Wages above this are outliers.
$101.4K - $113K
9% of jobs
$113K - $124.6K
6% of jobs
$124.6K - $136.1K
3% of jobs
$136.1K - $147.7K
3% of jobs
$147.7K - $159.2K
2% of jobs
$159.2K - $170.8K
1% of jobs
$43.6K
$95K
$170.8K
How much do cpu rtl design engineer jobs pay per year?
As of Sep 1, 2026, the average yearly pay for cpu rtl design engineer in Los Angeles, CA is $94,982.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,300.00 and $106,100.00 per year, depending on experience, location, and employer.
What is a CPU RTL design engineer?
CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?
To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.
What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?
CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Los Angeles, CA?
For Cpu Rtl Design Engineer jobs in Los Angeles, CA, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Los Angeles, CA look for?
The top searched job categories for Cpu Rtl Design Engineer jobs in Los Angeles, CA are:
What cities near Los Angeles, CA are hiring for Cpu Rtl Design Engineer jobs?
Cities near Los Angeles, CA with the most Cpu Rtl Design Engineer job openings:
Apple rating
8.1
Based on 680 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated DDR Design Engineer.
As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
Description
In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing
Design of state machines, data paths, arbitration and clock domain crossing logic
Logic synthesis, timing constraints
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Prior experience in DDR PHY design and mixed-signal environment is a plus
As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
Description
In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing
Design of state machines, data paths, arbitration and clock domain crossing logic
Logic synthesis, timing constraints
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Prior experience in DDR PHY design and mixed-signal environment is a plus
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976