We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
ASIC Digital Physical Design Manager
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Digital Physical Design Manager
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Digital Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Digital Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
Design Verification Engineer
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
Design Verification Engineer
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
Design Verification Engineer
Broomfield, CO · On-site
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
Design Verification Engineer
Broomfield, CO · On-site
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
Design Verification Engineer
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
Design Verification Engineer
$108K - $172K/yr
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...
FPGA Engineer
Englewood, CO · On-site
$130K - $165K/yr
FPGA Engineer Position Description : Protingent Staffing has an exciting direct hire FPGA Engineer ... Extensive knowledge with FPGA RTL design and development in System Verilog, Verilog, and/or VHDL
FPGA Engineer
Englewood, CO · On-site
$130K - $165K/yr
FPGA Engineer Position Description : Protingent Staffing has an exciting direct hire FPGA Engineer ... Extensive knowledge with FPGA RTL design and development in System Verilog, Verilog, and/or VHDL
Mixed Signal Digital Design Lead
Fort Collins, CO · On-site
$134K/yr
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs. * Logic Design: Design complex digital control loops ...
Mixed Signal Digital Design Lead
Fort Collins, CO · On-site
$134K/yr
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs. * Logic Design: Design complex digital control loops ...
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs. * Logic Design: Design complex digital control loops ...
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs. * Logic Design: Design complex digital control loops ...
FPGA DSP Engineer
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
FPGA DSP Engineer
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
FPGA DSP Engineer
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
FPGA DSP Engineer
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... Proven programming proficiency in x86 assembly, C/C++, Perl, Ruby and Python languages along with ...
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... Proven programming proficiency in x86 assembly, C/C++, Perl, Ruby and Python languages along with ...
System Integration/Test Engineer
Colorado Springs, CO · On-site
$130K - $160K/yr
RTL Networks considers factors such as (but not limited to) scope and responsibilities of the ... systems through design, integration, implementation, and support. * Coordinate, develop, and ...
System Integration/Test Engineer
Colorado Springs, CO · On-site
$130K - $160K/yr
RTL Networks considers factors such as (but not limited to) scope and responsibilities of the ... systems through design, integration, implementation, and support. * Coordinate, develop, and ...
FPGA DSP Engineer with Security Clearance
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
FPGA DSP Engineer with Security Clearance
Fort Collins, CO · On-site
$143K - $191K/yr
This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ... Collaborate with the Battlespace Awareness engineering team to ensure design consistency and ...
Master Physical Design Engineering Lead (up to $800k pkg)
Fort Collins, CO · On-site
$134K - $138K/yr
San Jose, CA, Irvine, CA or Fort Collins, CO Introduction Are you a seasoned Engineer who excels at ... RTL development, front end verification, DRC, and logic synthesis Knowledge of DFT methods ...
Quick apply
Master Physical Design Engineering Lead (up to $800k pkg)
Fort Collins, CO · On-site
$134K - $138K/yr
San Jose, CA, Irvine, CA or Fort Collins, CO Introduction Are you a seasoned Engineer who excels at ... RTL development, front end verification, DRC, and logic synthesis Knowledge of DFT methods ...
Verification Engineer
$120K - $192K/yr
Develop Python-based behavioral models and validate designs by comparing them against RTL ... Knowledge of CPU, DDR, bus, network protocols, or DSP design * Experience with AI-assisted ...
Verification Engineer
$120K - $192K/yr
Develop Python-based behavioral models and validate designs by comparing them against RTL ... Knowledge of CPU, DDR, bus, network protocols, or DSP design * Experience with AI-assisted ...
Senior FPGA Engineer II
Littleton, CO · On-site
Work with the hardware design team on requirements. * Complete FPGA logic design, coding ... Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block ...
Senior FPGA Engineer II
Littleton, CO · On-site
Work with the hardware design team on requirements. * Complete FPGA logic design, coding ... Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block ...
System Integration/Test Engineer with Security Clearance
Colorado Springs, CO · On-site
$130K - $160K/yr
RTL Networks considers factors such as (but not limited to) scope and responsibilities of the ... systems through design, integration, implementation, and support. * Coordinate, develop, and ...
System Integration/Test Engineer with Security Clearance
Colorado Springs, CO · On-site
$130K - $160K/yr
RTL Networks considers factors such as (but not limited to) scope and responsibilities of the ... systems through design, integration, implementation, and support. * Coordinate, develop, and ...
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
... Engineer to join our VLSI team. What you will be doing * Plan & implement UVM verification ... RTL Design experience * Experience validating designs for Space Applications Benefits * Competitive ...
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
... Engineer to join our VLSI team. What you will be doing * Plan & implement UVM verification ... RTL Design experience * Experience validating designs for Space Applications Benefits * Competitive ...
As a Technical Staff Design Engineer in the Secure Computing Group at Microchip, you will be at the ... analysis for RTL, mask layout * Lab skills and hands-on experience with test equipment.
As a Technical Staff Design Engineer in the Secure Computing Group at Microchip, you will be at the ... analysis for RTL, mask layout * Lab skills and hands-on experience with test equipment.
Cpu Rtl Design Engineer information
See Colorado salary details
$42.6K - $53.9K
2% of jobs
$53.9K - $65.1K
11% of jobs
$71.2K is the 25th percentile. Wages below this are outliers.
$65.1K - $76.4K
23% of jobs
The median wage is $83.7K / yr.
$76.4K - $87.7K
22% of jobs
$87.7K - $99K
17% of jobs
$99.3K is the 75th percentile. Wages above this are outliers.
$99K - $110.3K
9% of jobs
$110.3K - $121.5K
6% of jobs
$121.5K - $132.8K
3% of jobs
$132.8K - $144.1K
3% of jobs
$144.1K - $155.4K
2% of jobs
$155.4K - $166.7K
1% of jobs
$42.6K
$92.7K
$166.7K
How much do cpu rtl design engineer jobs pay per year?
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?
What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?
What are CPU RTL Design Engineers?
$134K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 9 days ago
Keysight Technologies rating
8.1
Based on 20 frontline employees who took The Breakroom Quiz
40th of 141 rated electronics manufacturers
Job description
Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team.
The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.
Responsibilities
- Set and drive the technical strategy for digital IP, block-level design, verification, and full-chip integration—aligning architectural choices to product differentiation, schedule, and long-term reuse.
- Lead, mentor, and scale a high-performing organization of architects, RTL designers, and verification engineers; establish clear technical expectations and a culture of ownership and excellence.
- Own program delivery from concept through tapeout and into productization—planning resources, managing schedules and milestones, and proactively driving risk retirement and trade-off decisions.
- Influence outcomes across the broader silicon ecosystem by partnering tightly with physical design, DFT/test, IP, software/firmware, packaging, systems engineering, and foundry/OSAT partners.
- Establish and enforce robust quality and signoff discipline, including design reviews, coding standards, verification closure, timing and power closure, area/constraints management, and manufacturability/yield considerations.
- Build a world-class team: recruit and hire top talent, develop technical leaders, and manage performance and career growth to retain key capabilities.
- Manage the operating model for the team, including budget ownership, EDA/tool strategy, license planning, and vendor/partner selection.
- Drive continuous improvement in productivity and predictability through design flows, automation, CI/regression infrastructure, and disciplined IP reuse strategies.
Qualifications
Must-have Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 7+ years of digital IC/ASIC development experience, with demonstrated progression in technical leadership (people management experience preferred).
- Strong hands-on depth in RTL micro-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA/timing closure, and power/performance optimization.
Preferred Qualifications
- Deep expertise in modern verification, including constrained-random methodology, formal techniques, and acceleration/emulation.
- Working knowledge of the full silicon lifecycle and cross-functional handoffs, including physical design, DFT/scan, signoff flows, and foundry enablement.
- Proven ability to deliver complex programs to tapeout—building credible plans, managing dependencies and risk, and driving alignment across multiple teams.
- Proficiency with industry-standard EDA environments (e.g., Cadence and Siemens/Mentor) and productivity scripting/automation (Python, Tcl, and/or Ruby).
- Executive-level communication skills and strong stakeholder management—able to translate technical trade-offs into clear decisions and commitments.
- Sound judgment under schedule pressure, with a track record of prioritizing the right trade-offs while maintaining quality.
- Demonstrated people leadership strengths, including mentoring and coaching engineers, developing technical leaders, and building a strong team culture of accountability, learning, and engineering excellence.
ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
Most offers will be between the minimum and the midpoint of the Salary Range listed below.
MIN $151,000.00 - MAX $253,000.00
#LI-MO1
Note: For other locations, pay ranges will vary by region
US Employees may be eligible for the following benefits:
- Medical, dental and vision
- Health Savings Account
- Health Care and Dependent Care Flexible Spending Accounts
- Life, Accident, Disability insurance
- Business Travel Accident and Business Travel Health
- 401(k) Plan
- Flexible Time Off, Paid Holidays
- Paid Family Leave
- Discounts, Perks
- Tuition Reimbursement
- Adoption Assistance
- ESPP (Employee Stock Purchase Plan)
Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***
Qualifications:Must-have Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 7+ years of digital IC/ASIC development experience, with demonstrated progression in technical leadership (people management experience preferred).
- Strong hands-on depth in RTL micro-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA/timing closure, and power/performance optimization.
Preferred Qualifications
- Deep expertise in modern verification, including constrained-random methodology, formal techniques, and acceleration/emulation.
- Working knowledge of the full silicon lifecycle and cross-functional handoffs, including physical design, DFT/scan, signoff flows, and foundry enablement.
- Proven ability to deliver complex programs to tapeout—building credible plans, managing dependencies and risk, and driving alignment across multiple teams.
- Proficiency with industry-standard EDA environments (e.g., Cadence and Siemens/Mentor) and productivity scripting/automation (Python, Tcl, and/or Ruby).
- Executive-level communication skills and strong stakeholder management—able to translate technical trade-offs into clear decisions and commitments.
- Sound judgment under schedule pressure, with a track record of prioritizing the right trade-offs while maintaining quality.
- Demonstrated people leadership strengths, including mentoring and coaching engineers, developing technical leaders, and building a strong team culture of accountability, learning, and engineering excellence.
ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
Most offers will be between the minimum and the midpoint of the Salary Range listed below.
MIN $151,000.00 - MAX $253,000.00
#LI-MO1
Note: For other locations, pay ranges will vary by region
US Employees may be eligible for the following benefits:
- Medical, dental and vision
- Health Savings Account
- Health Care and Dependent Care Flexible Spending Accounts
- Life, Accident, Disability insurance
- Business Travel Accident and Business Travel Health
- 401(k) Plan
- Flexible Time Off, Paid Holidays
- Paid Family Leave
- Discounts, Perks
- Tuition Reimbursement
- Adoption Assistance
- ESPP (Employee Stock Purchase Plan)
Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***
Education:UNAVAILABLEEmployment Type: UNAVAILABLEWhat Keysight Technologies employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Keysight Technologies
Sourced by ZipRecruiter
Industry
Electrical equipment, appliance, and component manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Rosa, CA, US
Year founded
1937