FPGA Development Engineer
$121.80K - $156.50K/yr
PURPOSE We are seeking a mid-career FPGA Development Engineer to join our growing hardware ... Experience with RTL design in VHDL or Verilog. * Hands-on simulation and verification experience ...
$121.80K - $156.50K/yr
PURPOSE We are seeking a mid-career FPGA Development Engineer to join our growing hardware ... Experience with RTL design in VHDL or Verilog. * Hands-on simulation and verification experience ...
$121.80K - $156.50K/yr
PURPOSE We are seeking a mid-career FPGA Development Engineer to join our growing hardware ... Experience with RTL design in VHDL or Verilog. * Hands-on simulation and verification experience ...
Birmingham, AL · On-site
$121.80K - $156.50K/yr
PURPOSE We are seeking a mid-career FPGA Development Engineer to join our growing hardware ... Experience with RTL design in VHDL or Verilog. * Hands-on simulation and verification experience ...
Birmingham, AL · On-site
$121.80K - $156.50K/yr
PURPOSE We are seeking a mid-career FPGA Development Engineer to join our growing hardware ... Experience with RTL design in VHDL or Verilog. * Hands-on simulation and verification experience ...
$128.10K - $164.50K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$128.10K - $164.50K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$110.80K - $142.30K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$110.80K - $142.30K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Huntsville, AL · On-site
$128.10K - $164.50K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Huntsville, AL · On-site
$128.10K - $164.50K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
Huntsville, AL · On-site
$80K - $140K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · On-site
$80K - $140K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · Remote
$90.80K - $124.40K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · Remote
$90.80K - $124.40K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · On-site
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
Huntsville, AL · On-site
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Quick apply
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
Birmingham, AL · On-site
$140K - $200K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... CPU-only and ARM64 platforms), including C++ inference layers • Advance fusion-aware ML models ...
Birmingham, AL · On-site
$140K - $200K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... CPU-only and ARM64 platforms), including C++ inference layers • Advance fusion-aware ML models ...
The Technical Leader role in Performance Engineering involves guiding the architectural direction ... Design and implement novel ways to minimize Tetragon's CPU overhead and memory footprint • ...
The Technical Leader role in Performance Engineering involves guiding the architectural direction ... Design and implement novel ways to minimize Tetragon's CPU overhead and memory footprint • ...
Birmingham, AL · On-site
$132K - $160K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... What Sets You Apart Essential Qualifications · Advanced degree (MS/PhD) in Electrical Engineering ...
Quick apply
Birmingham, AL · On-site
$132K - $160K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... What Sets You Apart Essential Qualifications · Advanced degree (MS/PhD) in Electrical Engineering ...
Birmingham, AL · On-site
$132K - $160K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... What Sets You Apart Essential Qualifications • Advanced degree (MS/PhD) in Electrical Engineering ...
Birmingham, AL · On-site
$132K - $160K/yr
You'll design algorithms capable of distinguishing vessels, land, shoreline constructions, wakes ... What Sets You Apart Essential Qualifications • Advanced degree (MS/PhD) in Electrical Engineering ...
$36.7K - $46.4K
2% of jobs
$46.4K - $56.2K
11% of jobs
$61.3K is the 25th percentile. Wages below this are outliers.
$56.2K - $65.9K
23% of jobs
The median wage is $72.1K / yr.
$65.9K - $75.6K
22% of jobs
$75.6K - $85.3K
17% of jobs
$85.6K is the 75th percentile. Wages above this are outliers.
$85.3K - $95K
9% of jobs
$95K - $104.8K
6% of jobs
$104.8K - $114.5K
3% of jobs
$114.5K - $124.2K
3% of jobs
$124.2K - $133.9K
2% of jobs
$133.9K - $143.7K
1% of jobs
$36.7K
$79.9K
$143.7K
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
Birmingham, AL
$121.80K - $156.50K/yr
Full-time
Posted 17 days ago
PURPOSE
We are seeking a mid-career FPGA Development Engineer to join our growing hardware development team. The ideal candidate has hands-on experience designing, implementing, and verifying complex digital logic using Xilinx FPGAs and the Vivado tool suite, along with a strong background in simulation and verification methodologies. You will work closely with cross-functional teams to architect, develop, and optimize FPGA-based solutions for high-performance embedded systems.
ROLE AND RESPONSIBILITIES
PREFERRED SKILLS, QUALIFICATIONS AND EDUCATION REQUIREMENTS
ADDITIONAL NOTES
What We Offer