Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Have experience with VHDL, Verilog, or other FPGA development languages * Have developed novel ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Design Verification Engineer, TPU Cloud Compute
Sunnyvale, CA · On-site
$159K - $194K/yr
Experience with SystemVerilog/Verilog. Preferred qualifications: * Master's degree or PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Design Verification Engineer, TPU Cloud Compute
Sunnyvale, CA · On-site
$159K - $194K/yr
Experience with SystemVerilog/Verilog. Preferred qualifications: * Master's degree or PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
ASIC Design Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$116 - $166/hr
Experience with SystemVerilog/Verilog. Preferred Qualifications * Master's degree or PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
ASIC Design Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$116 - $166/hr
Experience with SystemVerilog/Verilog. Preferred Qualifications * Master's degree or PhD in ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...
Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Have experience with VHDL, Verilog, or other FPGA development languages. * Have experience in ... APL may offer bonuses or other forms of compensation per internal policy and/or contractual ...
Contractual Verilog information
See salary details
$19.47 - $25.13
2% of jobs
$25.13 - $30.79
5% of jobs
$30.79 - $36.45
3% of jobs
$36.45 - $42.11
0% of jobs
$42.11 - $47.77
6% of jobs
$52.90 is the 25th percentile. Wages below this are outliers.
$47.77 - $53.43
9% of jobs
$53.43 - $59.09
15% of jobs
The median wage is $60.55 / hr.
$59.09 - $64.75
35% of jobs
$64.75 - $70.41
9% of jobs
$70.41 - $76.07
8% of jobs
$76.07 - $81.73
8% of jobs
$19
$59
$81
How much do contractual verilog jobs pay per hour?
What is the difference between Contractual Verilog vs FPGA Designer?
| Aspect | Contractual Verilog | FPGA Designer |
|---|---|---|
| Credentials | Verilog proficiency, sometimes certifications in HDL | Verilog/VHDL expertise, FPGA design certifications |
| Work Environment | Contract-based, project-specific | Full-time or contract, design and development focus |
| Industry Usage | Used in hardware design, verification projects | Designing FPGA hardware, implementing digital systems |
Contractual Verilog professionals focus on writing and verifying Verilog code for specific projects, often on a contractual basis. FPGA Designers typically have broader responsibilities in designing, simulating, and implementing FPGA-based systems. While both roles require Verilog skills, FPGA Designers usually have more comprehensive design responsibilities and may hold additional certifications or experience in FPGA development.

Reverse Engineer for RF Systems with Security Clearance
Laurel, MD • On-site
Other
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 4 days ago
Job description
* Develop prototypes of novel signal processing approaches
* Work in teams to modify device firmware and software to communicate in alternative ways
* Operationalize developed code by thoroughly testing, documenting, and integrating with sponsor systems
* Propose promising ideas for internal and external funding opportunities
* Share and enhance knowledge by clearly articulating ideas through papers and presentations to government decision makers, team members, and senior management Qualifications You meet our minimum qualifications for the job if you... * Possess a Bachelor's in Computer Science, Electrical Engineering, Computer Engineering, or other degree relevant to the duties as described above
* Have at least 3 years of experience writing assembly language, C, or C++ code that runs directly on embedded systems or integrates with real-time operating systems (RTOSes)
* Have experience with protocol reverse engineering and complex communication systems
* Have extensive experience with digital signal processing algorithms and are capable of (and excited by!) hypothesizing, prototyping, and extracting data from waveforms
* Are an outstanding communicator in both written and verbal forms
* Are able to acquire a Secret level security clearance by your start date and can ultimately acquire a TS/SCI level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship. You'll go above and beyond our minimum requirements if you... * Have a Master's or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or related field
* Have 6+ years of relevant experience
* Have experience with VHDL, Verilog, or other FPGA development languages
* Have developed novel concepts based on analyzing wireless systems
* Have experience with field testing or leading technical teams
* Hold an active TS/SCI security clearance #LI-AG1 About Us Why Work at APL? The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates. At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers. All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact . The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis. Minimum Rate $100,000 Annually Maximum Rate $245,000 Annually
About Johns Hopkins University Applied Physics Laboratory
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Laurel, MD, US
Year founded
1942