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Contractual Semiconductor Test Engineering Jobs (NOW HIRING)

Efficient Computer

Test Engineer

San Jose, CA · On-site

Help define and mature internal test engineering capabilities over time What You Bring Required * 5+ years of semiconductor test engineering experience in a fabless or IDM environment * Hands-on DFT ...

Power Integrations

Staff Test Engineer

San Jose, CA · On-site

A minimum of 12 years semiconductor Test Engineering experience with analog-mixed signal products, DFT and test plan responsibility, production support, and new product introduction experience.

Semtech

Semiconductor Test Technician

Camarillo, CA

$40K - $88K/yr

The Test Technician works closely with Test Engineers and Product Engineers to set up test ... semiconductor, electronics manufacturing, or ATE environment * ESD handling and static control ...

Power Integrations

Staff Test Engineer

San Jose, CA · On-site

E xp e rie nce: • A minimum of 12 years semiconductor Test Engineering experience with analog-mixed signal products, DFT and test plan responsibility, production support, and new product ...

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Contractual Semiconductor Test Engineering information

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How much do contractual semiconductor test engineering jobs pay per hour?

As of Aug 23, 2026, the average hourly pay for contractual semiconductor test engineering in the United States is $44.24, according to ZipRecruiter salary data. Most workers in this role earn between $33.41 and $52.40 per hour, depending on experience, location, and employer.

What is the difference between Contractual Semiconductor Test Engineering vs Semiconductor Test Engineer?

AspectContractual Semiconductor Test EngineeringSemiconductor Test Engineer
CredentialsTypically requires a degree in electrical engineering or related field; certifications varySame as contractual role, often with additional certifications preferred
Work EnvironmentContract-based, project-specific, often in manufacturing or testing labsPermanent or long-term employment, in similar environments
Employer & Industry UsageUsed by companies hiring temporary or project-based test engineers in semiconductor industryFull-time employees working on semiconductor testing processes

Contractual Semiconductor Test Engineering involves temporary, project-based roles focusing on testing semiconductor devices, while Semiconductor Test Engineers are typically permanent staff responsible for ongoing testing processes. Both roles require similar skills and work environments, but contractual positions offer flexibility and short-term engagement.

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Contractual Semiconductor Test Engineering jobs near you
Infographic showing various Contractual Semiconductor Test Engineering job openings in the United States as of August 2026, with employment types broken down into 77% Full Time, 6% Temporary, 11% Contract, and 6% Nights. Highlights an 94% In-person, and 6% Hybrid job distribution, with an average salary of $92,027 per year, or $44.2 per hour.

Test Engineer

Efficient Computer

San Jose, CA • On-site

Full-time

Retirement

Posted 26 days ago

Job description

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution
Efficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.
The right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers. You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products.
What You Will Do
DFT Strategy and Pattern Development
  • Partner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program
  • Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequences
  • Develop and maintain STIL and PDL test program files for ATE execution
  • Drive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partners
  • Support setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initialization
  • Understand and define power rail sequencing requirements for ATE execution to ensure safe device bringup

ATE Bringup and Test Program Development
  • Develop and debug test programs on ATE platforms including Advantest and Teradyne systems
  • Execute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams
  • Characterize device behavior across voltage, temperature, and frequency corners
  • Support load board bring-up and interface hardware validation
  • Define and manage test flows including wafer probe, final test, and bin sort
  • Understand test time optimization strategies such as pattern flow sequencing to minimize unnecessary power cycles

OSAT and Supplier Coordination
  • Serve as the primary test engineering interface with OSAT partners and test houses
  • Manage test program handoff to OSAT including documentation, qualification, and acceptance criteria
  • Coordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF as required
  • Track and analyze yield data from probe and final test, escalate anomalies, and drive corrective actions
  • Support die traceability and OTP programming flows in production bin sort
  • Coordinate with supply chain and operations on test capacity planning and lot scheduling

Cross-Program Ownership
  • Own test engineering across multiple active chip programs simultaneously
  • Build scalable test infrastructure and documentation that carries forward to future programs
  • Contribute to DFT reviews, tapeout checklists, and test escape analysis
  • Help define and mature internal test engineering capabilities over time

What You Bring
Required
  • 5+ years of semiconductor test engineering experience in a fabless or IDM environment
  • Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan
  • Experience generating and validating STIL patterns and working with test pattern delivery packages
  • ATE test program development experience on Advantest or Teradyne platforms
  • Experience supporting wafer probe and final test at an OSAT or test house, including load board bringup
  • Familiarity with power sequencing requirements and DFT entry flows for ATE test program development
  • Ability to work directly with external design partners and OSAT suppliers to coordinate pattern delivery and test execution
  • Strong written and verbal communication skills - this role requires ongoing collaboration with external partners across multiple time zones

Preferred
  • Experience with embedded memory test including characterization and programming of non-volatile memory technologies
  • Exposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocols
  • Familiarity with DFT tools from major EDA vendors
  • Experience at a fabless startup or small team where test engineering scope is broad
  • Exposure to leading-edge process nodes at 28nm or below
  • Experience with ATE yield analysis and test time optimization
  • Scripting ability in Python or Perl for data analysis and test automation
  • Experience generating VCD from RTL simulation and porting to STIL format

We offer a competitive salary for this role, generally ranging from $150,000 to $190,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.
Why Join Efficient?
Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

Apply