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Contract Remote Verification Jobs (NOW HIRING)

HJ Staffing

Contract Specialist (Remote)

Houston, TX · Remote

... remote opportunity, we welcome your application! What You'll Do (Responsibilities) As a Contract ... Verify and validate file completeness, identifying and resolving any missing documentation.

My VA Support

Insurance Verification Specialist

$17.50 - $21.50/hr

Insurance Verification & Authorization Specialist This is a remote position. Only LATAM-based ... Contract: Service Provision- Independant Contractor Key Responsibilities: * Perform insurance ...

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How much do contract remote verification jobs pay per hour?

As of Jul 22, 2026, the average hourly pay for contract remote verification in the United States is $18.87, according to ZipRecruiter salary data. Most workers in this role earn between $16.35 and $20.19 per hour, depending on experience, location, and employer.
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Contract Remote Verification jobs near you
Infographic showing various Contract Remote Verification job openings in the United States as of July 2026, with employment types broken down into 33% Full Time, 33% Part Time, and 34% Contract. Highlights an 100% Remote job distribution, with an average salary of $39,247 per year, or $18.9 per hour.
Design Verification Engineer - Remote - Contract opportunity

Design Verification Engineer - Remote - Contract opportunity

Zodiac Solutions

Irvine, CA • Remote

$139K - $169K/yr

Contractor

Posted 29 days ago

Job description

Role – Design Verification Engineer

Location – Remote (must be aligned with PST time zone)

Duration- Contract opportunity

 Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.