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Contract Asic Design Engineer Jobs in Boston, MA

ASIC Design Engineer

Boston, MA · On-site

$130 - $210/hr

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

New

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...

ASIC Design Engineer

Andover, MA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

ASIC Design Engineer

Andover, MA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC Designer, you will be responsible ...

Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC Designer, you will be responsible ...

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Contract Asic Design Engineer information

See Boston, MA salary details

$102.1K

$163.2K

$219.5K

How much do contract asic design engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for contract asic design engineer in Boston, MA is $163,173.00, according to ZipRecruiter salary data. Most workers in this role earn between $142,900.00 and $195,600.00 per year, depending on experience, location, and employer.

What is the difference between Contract Asic Design Engineer vs Contract FPGA Design Engineer?

AspectContract Asic Design EngineerContract FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experienceBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience
Work EnvironmentSemiconductor companies, chip design firms, contract roles in hardware developmentSemiconductor companies, FPGA development firms, contract roles in hardware prototyping
Industry UsageUsed in chip manufacturing, integrated circuit design, hardware developmentUsed in prototyping, hardware acceleration, FPGA-based solutions

The main difference between a Contract Asic Design Engineer and a Contract FPGA Design Engineer lies in their focus areas. Asic engineers work on designing custom chips for mass production, while FPGA engineers develop flexible hardware solutions using programmable logic devices. Both roles require similar educational backgrounds and often overlap in industry applications, but their end goals and tools differ.

What are the most commonly searched types of Asic Design Engineer jobs in Boston, MA? The most popular types of Asic Design Engineer jobs in Boston, MA are:
What are popular job titles related to Contract Asic Design Engineer jobs in Boston, MA? For Contract Asic Design Engineer jobs in Boston, MA, the most frequently searched job titles are:
What job categories do people searching Contract Asic Design Engineer jobs in Boston, MA look for? The top searched job categories for Contract Asic Design Engineer jobs in Boston, MA are:
Infographic showing various Contract Asic Design Engineer job openings in Boston, MA as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 8% Part Time, and 6% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $163,173 per year, or $78.4 per hour.

ASIC Design Engineer

Conductor

Boston, MA • On-site

$130 - $210/hr

Other

Posted yesterday

New


Job description

We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.

Ideal Background:
  • Hands-on experience with multiple advanced node tapeouts
  • Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
  • Understanding of PPA improvement and what levers exist for each level of the stack
  • Ability to think creatively about methodology for fast design iterations
Nice to Have:
  • Hands-on experience with ASIC design process for large die (ideally reticle max) chips
  • Hands-on experience with ASIC design process for AI chips
  • Hands-on experience with multi-die/multi-chiplet/MCM designs
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