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Compact Device Modeling Jobs in California (NOW HIRING)

OSI Engineering, Inc.

Gear Design SME

Sunnyvale, CA · On-site

$80 - $95/hr

A globally leading consumer device company based in Sunnyvale, CA is seeking a highly skilled Gear ... This role will drive innovation in compact mechanical drive systems for next-generation consumer ...

Apple

Biomedical Research Engineer

Cupertino, CA

$184K - $324K/yr

... in a compact form-factor, thus enabling the next-generation of optical health sensors. The ... The candidate must be able to employ simulation tools to develop models of sensor behavior. Lastly ...

Apple

Biomedical Research Engineer

Cupertino, CA

$129K - $225K/yr

... in a compact form-factor, thus enabling the next-generation of optical health sensors. The ... The candidate must be able to employ simulation tools to develop models of sensor behavior. Lastly ...

Pivotal

Staff Power Electronics Engineer

Palo Alto, CA · On-site

$131K - $155K/yr

Efficient, compact, and simple, Pivotal aircraft are designed for a wide range of consumer, public ... loss modeling * System understanding of device characteristics, gate driving circuit design ...

Pivotal

Staff Power Electronics Engineer

Palo Alto, CA · On-site

$131K - $155K/yr

Efficient, compact, and simple, Pivotal aircraft are designed for a wide range of consumer, public ... loss modeling * System understanding of device characteristics, gate driving circuit design ...

Pivotal

Staff Power Electronics Engineer

Palo Alto, CA · On-site

$180K - $210K/yr

Efficient, compact, and simple, Pivotal aircraft are designed for a wide range of consumer, public ... loss modeling * System understanding of device characteristics, gate driving circuit design ...

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All JobsCompact Device Modeling JobsCompact Device Modeling Jobs in California

Compact Device Modeling information

What are the key skills and qualifications needed to thrive as a Compact Device Modeling Engineer, and why are they important?

To thrive as a Compact Device Modeling Engineer, you need a strong background in semiconductor physics, device modeling, and typically an advanced degree in electrical engineering or a related field. Proficiency with simulation tools like SPICE, TCAD software, and programming languages such as Python or MATLAB, as well as knowledge of industry-standard modeling languages (e.g., Verilog-A), is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with cross-functional teams and interpret complex data. These skills are crucial for developing accurate models that drive innovation and reliability in semiconductor device design.

What types of teams or departments does a Compact Device Modeling engineer typically collaborate with?

Compact Device Modeling engineers often work closely with circuit design teams, process technology groups, and EDA (Electronic Design Automation) tool developers. Collaboration is essential because accurate device models are critical for reliable circuit simulations and successful chip fabrication. Regular communication with these departments ensures that the models reflect real-world device behavior and are compatible with evolving design requirements and manufacturing technologies. This cross-functional teamwork provides valuable exposure to multiple aspects of semiconductor development and can open doors for broader career growth.

What is compact device modeling?

Compact device modeling is the process of creating simplified mathematical models that accurately represent the electrical behavior of semiconductor devices, such as transistors, within electronic circuits. These models are essential for circuit simulation tools, enabling engineers to predict circuit performance without resorting to complex, time-consuming physical simulations. Compact models balance accuracy and computational efficiency, making them a cornerstone in the design and verification of integrated circuits.

What is the difference between Compact Device Modeling vs Semiconductor Device Engineer?

AspectCompact Device ModelingSemiconductor Device Engineer
CredentialsTypically requires engineering degree, specialized modeling certificationsRequires engineering degree, often with additional certifications in device physics
Work EnvironmentResearch labs, simulation centers, R&D departmentsDesign labs, manufacturing facilities, R&D teams
Industry UsageUsed for device simulation, circuit design, and performance predictionInvolved in device development, fabrication, and testing

Compact Device Modeling focuses on creating simplified models of semiconductor devices for simulation purposes, aiding circuit design. Semiconductor Device Engineers work on designing, developing, and testing actual semiconductor devices. While both roles require engineering expertise and involve semiconductor technology, modeling is more simulation-oriented, whereas engineering involves hands-on device development.

What are popular job titles related to Compact Device Modeling jobs in California? For Compact Device Modeling jobs in California, the most frequently searched job titles are:
What job categories do people searching Compact Device Modeling jobs in California look for? The top searched job categories for Compact Device Modeling jobs in California are:
What cities in California are hiring for Compact Device Modeling jobs? Cities in California with the most Compact Device Modeling job openings:
Compact Device Modeling jobs near you
Sr. Staff Engineer, Electrical Link Architecture

Sr. Staff Engineer, Electrical Link Architecture

Ayar Labs

San Jose, CA • On-site

$190K - $223K/yr

Full-time

Re-posted 20 days ago

Job description

Sr. Staff Engineer, Electrical Link Architecture
Location: San Jose, CA (on-site)
Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co-packaged optics (CPO), we develop silicon photonics solutions that deliver unprecedented bandwidth density and reach, at a fraction of the power consumption required to scale next-generation AI models.
Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Joining our Link Design and Architecture team, you will own the electrical-side modeling that drives our silicon photonics I/O platform - the analog front end, the DSP that closes the link, and the models that make circuits and photonics co-simulate end-to-end. This team is responsible for the robustness and performance of the optical links that power our technology, from component-level modeling through architecture definition, full link analysis, specification development, and yield prediction. Beyond today's products, the team drives the exploration of next-generation link architectures and directly shapes our long-term technology roadmaps.
Essential Functions
  • Build and maintain compact models of the analog front end and the DSP chain at the fidelity needed for accurate BER and link-margin prediction.
  • Co-design Verilog-A models of the electrical/optical interface - modulators, photodetectors, and the blocks where circuits and photonics meet - with analog / mixed-signal (AMS) designers.
  • Anchor models to silicon by working with validation engineers to reconcile simulation against measurement.
  • Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
  • Collaborate across AMS, photonics, and validation to keep the modeling stack coherent with the product roadmap.
  • Run end-to-end link simulations to evaluate device and architecture choices, informing current product design and future roadmap exploration.

Required Qualifications
  • BS in Electrical Engineering, Physics, or a related field.
  • 5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
  • Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
  • Proficiency in Verilog-A and mixed-signal simulation methodologies.
  • Experience with statistical circuit analysis methods (corners, Monte Carlo).
  • Strong Python skills for scientific computing and data analysis.

Preferred Qualifications
  • Prior industry experience architecting and deploying SerDes into a shipping product.
  • MS or Ph.D in Electrical Engineering, Physics, or a related field.
  • Hands-on experience with silicon bring-up, validation, or link characterization.
  • Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
  • Familiarity with Cadence Virtuoso / ADE / Spectre.
  • Familiarity with optical transceiver principles, modulation formats, and industry standards.

Salary range: $190,000 - $223,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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